for Electrostatic DischargeSensitivity Testing –
Charged Device Model (CDM)Component Level
™
Electrostatic Discharge Association7900 Turin Road, Bldg.3, Suite 2
Rome, NY 13440-2069
An American National Standard Approved May 2, 2001
Approved September 26, 1999ESD Association
™
ESD-STM5.3.1-1999
for Electrostatic Discharge
Sensitivity Testing
Charged Device Model (CDM) -Component Level
ESD Association Standard Test Method
CautionNotice
ESD Association standards and publications are designed to serve the publicinterest by eliminating misunderstandings between manufacturers and
purchasers, facilitating the interchangeability and improvement of products andassisting the purchaser in selecting and obtaining the proper product for hisparticular needs. The existence of such standards and publications shall not inany respect preclude any member or non-member of the Association frommanufacturing or selling products not conforming to such standards and
publications. Nor shall the fact that a standard or publication is published by theAssociation preclude its voluntary use by non-members of the Associationwhether the document is to be used either domestically or internationally.
Recommended standards and publications are adopted by the ESD Associationin accordance with the ANSI Patent policy.
Interpretation of ESD Association Standards: The interpretation of standards in-so-far as it may relate to a specific product or manufacturer is a proper matterfor the individual company concerned and cannot be undertaken by any personacting for the ESD Association. The ESD Association Standards Chairman maymake comments limited to an explanation or clarification of the technical
language or provisions in a standard, but not related to its application to specificproducts and manufacturers. No other person is authorized to comment onbehalf of the ESD Association on any ESD Association Standard.
Published by:
Electrostatic Discharge Association7900 Turin Road, Building 3, Suite 2Rome, NY 13440-2069
Copyright © 1999 by ESD AssociationAll rights reserved
No part of this publication may be reproduced in any form, inan electronic retrieval system or otherwise, without the priorwritten permission of the publisher.
Printed in the United States of America
ISBN: 1-58537-011-8
(This foreword is not part of ESD Association Standard Test Method STM5.3.1-1999)
Foreword
Existing electrostatic discharge (ESD) test models and standards model a charged object approaching a
component and discharging through the component. However, with the increasing use of automated component handling systems another potentially destructive discharge mechanism, the Charged Device Model (CDM), becomes increasingly important. In the charged device model the component itself becomes charged - usually by sliding on a surface - and is rapidly discharged by (an ESD event) as it approaches a conductive object.
Accurately quantifying the CDM discharge event is very difficult, if not impossible, due to the limitations of the measuring equipment and its influence on the discharge itself. The CDM discharge is generally completed in a few nanoseconds, and peak currents of tens of amperes have been observed. The peak current into the
component will vary considerably depending on a large number of factors such as: package type and parasitics. The typical failure mechanism for the CDM model, observed in MOS components, is dielectric damage, although other damage has been noted.
The CDM sensitivity of a given component is very package dependent. The same integrated circuit (IC) chip in a small outline package (SOP) may be more susceptible to CDM damage than it is in a dual-in-line (DIL) package. ICs in thin small outline packages (TSOP), or a pin grid array (PGA) packages usually have the lowest CDM withstand voltage.
Based on results obtained with early CDM testers, which did not necessarily meet the waveforms specified in this standard, components with CDM sensitivities of 500 volts or less proved difficult to handle without damage. Components with CDM sensitivities of 1,500 volts or more did not experience major field problems using proper handling techniques.
This document does not apply to the so-called SDM testers: socketed discharge model. Waveform parameters for the 30 pF verification module should be used for guidance only. They may be subject to change in future revisions of this document.
This Standard Test Method was processed and approved for submittal to the ESD Association Standards Committee and the Association Board of Directors by the Device Testing Working Group, 5.0.
At the time this standard was approved the Working Group had the following members:
Jon Barth Barth Electronics Tom Diep Texas Instruments
Marti Farris
Intel
Mark Kelly
Delphi Delco Electronics Systems
Koen Verhaege, Chair Sarnoff Corporation
Lou DeChairo Lucent Technologies
Mike Chaine Micron Technology Leo G. Henry
ORYX Instruments Corporation
Hugh Hyatt Hyger Physics Thomas Meuse
Keytek Scott Johnson
AMD Joseph Veltri
Ford
Ira Cohen Intel
Bob Carey
Lucent Technologies
Ian Morgan AMD
In addition the following people made significant contributions to this document:
Satoshi Isofuku
Tokyo Electronics Trading Les Avery
Sarnoff Corporation
Terry Welsher Lucent Technologies
Karlheinz Bock
IMEC
i
Table of Contents
1. SCOPE AND PURPOSE..............................................................................................................................1 1.1 SCOPE..........................................................................................................................................................1 1.2 PURPOSE......................................................................................................................................................1 2. REFERENCES..............................................................................................................................................1 3. DEFINITIONS................................................................................................................................................1 3.1 CHARGED DEVICE MODEL...............................................................................................................................1 3.2 CDM ESD TESTER........................................................................................................................................1 3.3 CONTACT-MODE DISCHARGE............................................................................................................................1 3.4 NON-CONTACT MODE DISCHARGE....................................................................................................................1 3.5 COMPONENT.................................................................................................................................................1 3.6 COMPONENT FAILURE.....................................................................................................................................1 3.7 ELECTROSTATIC DISCHARGE SENSITIVITY (ESDS).............................................................................................1 3.8 ESD WITHSTAND VOLTAGE.............................................................................................................................1 4. ESD COMPONENT CLASSIFICATIONS......................................................................................................1 5. COMPONENT CHARGING AND DISCHARGING METHODS......................................................................2 5.1 DIRECT CHARGING METHOD............................................................................................................................2 5.2 FIELD-INDUCED METHOD.................................................................................................................................2 5.3 DISCHARGING METHODS.................................................................................................................................2 6. REQUIRED EQUIPMENT..............................................................................................................................3 6.1 CDM ESD TESTER.......................................................................................................................................3 6.2 WAVEFORM VERIFICATION EQUIPMENT.............................................................................................................3 6.2.1 Equipment for 3.5 Gigahertz Waveform Measurement...........................................................................3 6.2.2 Equipment for 1 Gigahertz Waveform Measurement..............................................................................3 6.2.3 Verification Standard Test Modules for CDM Testing.............................................................................3 6.2.4 Capacitance Meter................................................................................................................................3 7. PERIODIC EQUIPMENT CALIBRATION, TESTER QUALIFICATION, WAVEFORM RECORDS, AND
WAVEFORM VERIFICATION REQUIREMENTS..............................................................................................3 7.1 EQUIPMENT CALIBRATION...............................................................................................................................3 7.1.1 Verification Modules..............................................................................................................................4 7.2 TESTER QUALIFICATION..................................................................................................................................4 7.3 TESTER WAVEFORM RECORDS - NEW EQUIPMENT...........................................................................................4 7.4 TESTER WAVEFORM VERIFICATION..................................................................................................................4 8. QUALIFICATION AND VERIFICATION PROCEDURES...............................................................................4 8.1 CDM ESD TESTER QUALIFICATION PROCEDURE..............................................................................................4 8.2 WAVEFORM VERIFICATION PROCEDURE............................................................................................................5 9. CDM ESDS TESTING TEQUIREMENTS AND PROCEDURES....................................................................6 9.1 TEST REQUIREMENTS.....................................................................................................................................6 9.1.1 Handling of Components.......................................................................................................................6 9.1.2 ESD Stress Test Temperature...............................................................................................................6 9.1.3 Recommended Waveform Check..........................................................................................................6 9.1.4 Component Static and Dynamic Tests...................................................................................................6 9.2 CDM COMPONENT CLASSIFICATION TESTING PROCEDURE................................................................................6 10. CLASSIFICATION CRITERIA.....................................................................................................................7 11. APPENDIX 1: VERIFICATION MODULES FOR CDM TESTING..............................................................11
ii
12. APPENDIX 2: DISCHARGE TEST METHOD GUIDANCE........................................................................12 12.1 NON-CONTACT MODE DISCHARGE...............................................................................................................12 12.2 CONTACT MODE DISCHARGE.......................................................................................................................11 13. APPENDIX 3: RECOMMENDED COMPONENT, VERIFICATION MODULE AND TESTER CLEANING
METHOD.........................................................................................................................................................13
Table of Figures
FIGURE 1: CDM ESD WAVEFORM FOR THE VERIFICATION MODULES, USING A 3.5 GIGAHERTZ BANDWIDTH MEASUREMENT
SYSTEM........................................................................................................................................................8 FIGURE 2: CDM ESD WAVEFORM FOR THE STANDARD VERIFICATION MODULES USING THE ONE GIGAHERTZ BANDWIDTH
MEASUREMENT SYSTEM.................................................................................................................................9 FIGURE 3: 30 PF VERIFICATION MODULE WITH 26 MM DISK.....................................................................................11 FIGURE 4: 4 PF VERIFICATION MODULE WITH 9 MM DISK.........................................................................................11
Table of Tables
TABLE 1 - CDM ESD CLASSIFICATION LEVELS.......................................................................................................2 TABLE 2 - ESD STEP STRESS LEVELS...................................................................................................................5
iii
ESD Association Standard Test Method ESD-STM5.3.1-1999
ESD Association Standard Test
Method for Electrostatic Discharge Sensitivity Testing -
CHARGED DEVICE MODEL (CDM), COMPONENT LEVEL
1. Scope and purpose
1.1 Scope
This standard establishes the procedure for testing, evaluating and classifying the
electrostatic discharge (ESD) sensitivity of components to the defined charged device model (CDM).
1.2 Purpose
To establish a correlatable test method that
simulates CDM failures and provides reliable and repeatable results from tester to tester. This will allow accurate comparisons of component CDM ESD sensitivity levels.
2. References
EOS/ESD-ADV1.0, Glossary of Terms1
3. Definitions
For the purposes of this standard the following definitions shall apply in addition to those specified in the ESD Association Glossary of Terms.
3.1 Charged Device Model
A model that approximates the discharge event that occurs as a charged component discharges to another object at a different electrostatic potential.
3.2 CDM ESD tester
Equipment (referred to as \"tester\" in this
standard) that simulates the component level Charged Device Model ESD event using the non-socketed test method.
1
ESD Association, 7900 Turin Road, Bldg 3, Ste 2, Rome, NY, 13440-2069, 315-339-6937
3.3 Contact-mode discharge
An ESD event initiated within a relay. The relay is connected to the component pin via a probe, and the component is not in a socket. 3.4 Non-contact mode discharge
An ESD event that is initiated by a probe tip approaching a component pin and the component is not placed in a socket. 3.5 Component
An item such as a resistor, diode, transistor, integrated circuit or hybrid
3.6 Component failure
A condition in which a component fails to meet one or more specified static or dynamic data sheet parameters.
1. Static parameters are those measured with
the component in a non-operating (standby) condition. These parameters may include, but are not limited to: input leakage current, input breakdown voltage, output high and low voltages, output drive current, and supply current.
2. Dynamic parameters are those measured
with the component in a functioning
(operating) condition. These parameters may include, but are not limited to: full
functionality, output rise and fall times under a specified load condition, and dynamic current draw. 3.7 Electrostatic discharge sensitivity (ESDS) The ESD level that causes component failure. 3.8 ESD withstand voltage
The maximum ESD level that does not cause component failure.
4. ESD Component Classifications
ESD sensitive components are classified
according to their ESD withstand voltage using the test procedure described in this standard. The CDM ESD component classification levels are shown in Table 1.
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ESD-STM5.3.1-1999
Table 1 - CDM ESD Classification Levels Class Voltage range C1 <125 v C2 125 v to <=250 v C3 250 v to <=500 v C4 500 v to <=1000 v C5 1000 v to <=1500 v C6 1500 v to <=2000 v C7 =>2000 v
Note 1: Use the \"C\" prefix to indicate a CDM classification.
Note 2: Add the following Suffix codes:
c = contact mode
n = non-contact mode For example:
C4n: CDM, class 4, non-contact mode
5. Component Charging and Discharging Methods
Either of the following two methods may be used to raise the component potential for the subsequent CDM discharge.
5.1 Direct Charging Method
The component to be tested is placed on the ground plate and charged through the pin which best provides an ohmic connection to the
substrate or bulk material of the component, or through all pins simultaneously. The total charging resistance shall be at least 100 megohms. To prevent component damage,
precautions shall be taken to ensure the charging mechanism and component are at ground
potential prior to the initial connection. At least one megohm of the charging resistance shall be physically placed close to the charging pin to isolate the effect of any residual charge on the charge up line. Contact to the charging pin(s) must be established before the voltage is raised. Each pin is discharged, one at a time (including power supply pins and ground pins), except the pins connected to the substrate. Re-charge the component after each pin has been discharged. It is permissible to leave the charging probe on the charging pin during the discharge cycle
provided the waveform requirements of Section 7 are satisfied.
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Note 3: The substrate, or bulk material, is typically called Vss, or ground, for NMOS or for n-well (p-substrate) CMOS
technologies; and Vcc, or Vdd, for p-well (n-substrate) CMOS technologies. For a charge-pumped substrate (where there is no direct access through an external pin), the Vss or ground pin is still appropriate to use.
5.1.1 Multi-chip modules or other special
components (e.g., Silicon on Sapphire, Silicon on insulator, and hybrids) must be charged through a common power supply pin or simultaneously through multiple pins to ensure the entire component reaches the charging potential.
5.1.2 If the process technology is unknown,
charge the component through the Vss or ground pin, or through all pins
simultaneously. Make note of the charging pins when reporting the results. Vpp pins shall never be used as charging pins, unless all device pins are simultaneously contacted and charged.
5.2 Field-induced Method
Place the component to be tested on the charging plate. Raise the potential of the component by energizing the field charging plate. Discharge through all pins, including Vcc and Vss, one at a time. The size of the field charging plate, at least 7 times larger in area than the size of the component under test, shall be such that the waveform qualification meets the requirement of Section 7. The total source resistance of the charging plate shall be at least 100 megohm. The thickness of the dielectric
covering the charge plate shall have a maximum thickness of 130 microns as the presence of the dielectric reduces the package capacitance between the component and the charging plate which affects the discharge current. Take precautions to ensure components are not charged prior to testing.
5.3 Discharging Methods
Background information on discharging methods is given in Appendix 2.
ESD-STM5.3.1-1999
6. Required Equipment
6.1 CDM ESD Tester
Equipment meeting the requirements of this standard, producing pulses meeting the
waveform characteristics specified in figure 1 and figure 2.
Note 4: Minimize parasitics in the charge and discharge paths when
constructing test equipment. Parasitics greatly influence test results.
6.2 Waveform Verification Equipment
6.2.1 Equipment for 3.5 Gigahertz Waveform Measurement
6.2.1.1 Oscilloscope - An oscilloscope or
transient digitizer with a single shot 3 dB-bandwidth of at least 3.5 gigahertz (e.g., an Tektronix SCD 5000 or equivalent) with a nominal 50 ohm input impedance.
6.2.1.2 Attenuator - with a precision of 0.1 dB at
3.5 gigahertz a DC precision of the attenuation factor of 5% and an impedance of 50 ±3 ohms.
6.2.1.3 Probe - An inductive current transducer
or coaxial resistive probe of at least 5 gigahertz bandwidth.
6.2.1.4 Cable assemblies - Cable assemblies
with no more than 0.4 dB loss at frequencies up to 3.5 gigahertz and impedance of 50 ±2 ohms. 6.2.2 Equipment for 1 Gigahertz Waveform Measurement
6.2.2.1 Oscilloscope - An oscilloscope or
transient digitizer with a single shot
bandwidth of at least one gigahertz.(e.g., a Tektronix SCD 1000, or Tektronix 7104, or equivalent) with a nominal 50 ohm input impedance.
6.2.2.2 Attenuator - Attenuator with a precision
of ±0.1 dB at 1.0 gigahertz, a DC
precision of the attenuation factor of 5% and an impedance of 50 ±3 ohms.
6.2.2.3 Probe - An inductive current transducer
or coaxial resistive probe of at least 5 gigahertz bandwidth.
6.2.2.4 Cable Assemblies - Cable assemblies
with no more than 0.1 dB loss at frequencies up to 1.0 gigahertz and impedance of 50 ±2 ohms.
6.2.3 Verification Standard Test Modules for CDM Testing
Two gold-plated or nickel-plated etched copper disks on single sided 0.8 millimeter thick FR-4 circuit board material. Each disk shall be etched in the center of a square of material at least 30 millimeters by 30 millimeters. The larger disk shall have a capacitance of 30 pF ±5% at 1 megahertz (approximately 26 millimeters in diameter). The smaller disk shall have a capacitance of 4 pF ±5% at 1 megahertz
(approximately 9 millimeters in diameter). The capacitance is measured with the non-metallized non-disc side of the verification modules in intimate contact with the metal surface of a ground plane. The verification modules are shown in Figures 3 and 4 (see Appendix 1).
Note 5: It is very important that the verification standard test modules are compliant with the specifications in section 6.2.3. Therefore, one must measure the capacitance at 1MHz as specified. If the modules do not comply, they can not be used.
6.2.4 Capacitance Meter
Capacitance meter with a resolution of 0.2 pF, a measurement accuracy of 3%, and a
measurement frequency of one megahertz.
Note 6: The sampling rate of a digitized sampling oscilloscope may affect the waveform.
7. Periodic Equipment Calibration,
Tester Qualification, Waveform Records, and Waveform Verification Requirements
7.1 Equipment Calibration
Calibrate all equipment used for tester or waveform verification in accordance with the manufacturers' recommendations, with a
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ESD-STM5.3.1-1999
maximum of one year between calibrations. This equipment list includes oscilloscope, attenuator, current transducer, coaxial resistive probe, capacitance meter, and calibration module(s) conforming to the requirements of 6.2. Calibration shall be traceable to national standards, such as National Institute of
Standards and Technology (NIST) in the United States, or international standards.
7.1.1 Verification Modules
7.1.1.1 Place the non-metallized non-disc side
of the 4 pF verification module in
intimate contact with the metal surface of a ground plane. Ensure there is no air space between the module and the ground plane.
7.1.1.2 Measure the capacitance of the module
to the ground plane using the
capacitance meter. The capacitance value of the verification module shall be within the value specified in 6.2.3.
7.1.1.3 Repeat from 7.1.1.1 using the 30 pF
verification module on the ground plane.
7.1.1.4 Measure the capacitance of the module
to the ground plane using the
capacitance meter. The capacitance value of the verification module shall be within the value specified in 6.2.3.
7.2 Tester Qualification
Perform the CDM ESD tester qualification as part of the initial acceptance testing and routinely as suggested by the manufacturer. The
maximum period between full qualification tests shall be one year. In addition, repeat qualification testing whenever the equipment is serviced in a manner which the manufacturer or user defines as having the potential for modifying discharge current waveforms. The CDM ESD tester qualification procedure is specified in 8.1. Periodic waveform verification shall be performed in accordance with 7.4.
Note 7: Due to the high cost of the waveform monitoring equipment,
manufacturer certified discharge heads may be used and waveform verification performed using a lower bandwidth monitor as specified in 6.2.2.
4
7.3 Tester Waveform Records - New Equipment
Record positive and negative waveforms (using either photographs or digitized waveforms)
during the tester initial qualification procedures. Waveform records are required for charge levels as defined in the tester qualification procedure. Retain the waveform records until the next calibration or for the duration specified by the internal record keeping procedures.
7.4 Tester Waveform Verification
Verify and record the ESD tester waveforms periodically, using the verification modules defined in 6.2.3. The maximum time between verifications shall be one month for equipment that is in use for at least 30 hours per week, or up to three months for testers used less
frequently. Verification shall include waveform observations and comparison to waveform
records for both positive and negative polarities. The waveform verification procedure is given in 8.2.
Dielectric layers and discharge contacts (e.g., pogo pins) are key elements of the tester
construction. Any change to these requires tester waveform verification.
8. Qualification and Verification Procedures
For the purpose of both equipment qualification and waveform verification, the standard
verification modules are treated as components.
8.1 CDM ESD Tester Qualification Procedure
CDM ESD tester qualification shall ensure waveform integrity of the discharge current for both positive and negative polarities, and each verification module specified in 6.2.3. Monitor the waveform using the full bandwidth
oscilloscope, attenuator, current probe or coaxial resistive probe described in 6.2.1. Do not use the one-gigahertz monitoring equipment for tester qualification.
8.1.1 Clean the verification modules. Avoid skin
contact with the modules prior to and
during testing. A recommended procedure is described in Appendix 3.
ESD-STM5.3.1-1999
8.1.2 Clean tester components to remove any
surface contamination that could result in charge loss. Pay particular attention to the discharge probe, charging probe, and the ground plane on which the device is placed. A recommended procedure is described in Appendix 3.
8.1.3 Place the 30 picofarad (pF) verification
module on the ground plane or charging plate, ensuring intimate contact (no air space) between the module and the ground plane. When a dielectric layer is used for component testing, it must meet the requirements specified in section 5 and be present during the calibration procedure.
8.1.4 Set the horizontal time scale of the
oscilloscope to 0.5 nanoseconds per division. Set the oscilloscope vertical sensitivity and offset, using attenuators if necessary, to cover the center 80% of the full scale deflection.
8.1.5 Raise the potential of the module, or
charging plate, to positive 500 volts.
8.1.6 Discharge the module with the discharge
probe close to the center of the verification module and record the discharge current waveform. All parameters shall be within the limits specified in figure 1. Record the waveform.
8.1.7 Repeat the procedure given in 8.1.5 and
8.1.6 at least two more times. Save the record for future verifications. (Record all and save the one closest to the mean for future verification.)
8.1.8 Repeat the procedure given in 8.1.5
through 8.1.7 using a negative 500 volt charging potential.
8.1.9 For the 4 picofarad verification module,
repeat 8.1.4 through 8.1.8 using all the voltage levels in table 2. If the maximum potential of the tester is lower than 2000 volts, use that as the maximum. Set the oscilloscope vertical sensitivity and offset, using attenuators if necessary, to cover the center 80% of the full-scale deflection for each voltage level. All parameters shall be within the limits specified in figure 1. Save these records for future verifications.
8.1.10 It is recommended that all waveform
records be supplied with the tester for future waveform verification purposes. Table 2 - ESD Step Stress Levels
Level Charging Voltage 1 125 v 2 250 v 3 500 v 4 1000 v 5 1500 v 6
2000 v
8.2 Waveform verification procedure
Waveform verification shall ensure waveform integrity of the discharge current, as specified in this standard, for both positive and negative polarities, using the small 4 pF verification module specified in 6.2.3.
If the one-gigahertz bandwidth monitoring equipment will be used for future waveform verification, repeat the CDM ESD tester
qualification procedure using the one-gigahertz bandwidth oscilloscope. Record the waveforms for future comparison purposes during waveform verification.
8.2.1 Clean the 4 pF verification module. Avoid
further skin contact with the module prior to and during testing. A recommended procedure is described in Appendix 3.
8.2.2 Clean the tester to remove any surface
contamination that could result in charge loss. Pay particular attention to the discharge probe, charging probe, the ground plane on which the device is placed. A recommended procedure is described in Appendix 3.
8.2.3 Place the 4 pF verification module on the
ground plane or charging plate, ensuring intimate contact (no air space) between the module and the ground plane. When a dielectric layer is used for component testing, it must meet the requirements specified in section 5 and be present during the calibration procedure.
8.2.4 Set the horizontal time scale of the
oscilloscope to 0.5 nanoseconds per
division, and set the vertical sensitivity to allow for approximately ten amperes full scale deflection.
5
ESD-STM5.3.1-1999
8.2.5 Raise the potential of the module, or
charging plate, to positive 500 volts.
8.2.6 Discharge the module and observe the
current waveform. All parameters shall be within the limits specified in figure 1 if the 3.5 gigahertz waveform monitoring equipment is used. If the narrower bandwidth waveform monitoring equipment is used, ensure that all
parameters are within the limits specified in figure 2. It is recommended that the waveform parameters be compared to the previous satisfactory verification record. Changes in the shape of the discharge pulse, even though they are within
specification, may indicate degradation of the discharge path.
8.2.7 Repeat the procedure given in 8.2.5
through 8.2.6 using a negative 500 volt charging potential and evaluate the waveform.
8.2.8 Remove the verification module.
9. CDM ESDS Testing Requirements and Procedures
9.1 Test requirements
9.1.1 Handling of Components
Use ESD prevention procedures before, during and after testing.
9.1.2 ESD Stress Test Temperature
Stabilize the component to room temperature prior to and during the ESD stress testing period.
9.1.3 Recommended Waveform Check
At the beginning and end of each shift during which testing is performed, ensure waveform integrity for the discharge head for the 500 volt level of table 2, for positive and negative
polarities, using the 4 pF verification module. If the waveforms no longer meet the specified limits (see figure 1 or figure 2), all test results subsequent to the previous satisfactory check shall be considered invalid. If testing is performed in consecutive shifts, waveform
checks at the end of one shift may also serve as the initial checks for the following shift.
6
9.1.4 Component Static and Dynamic Tests
Perform, full static and dynamic testing to
specified component data sheet parameters prior to and following ESD stress testing to determine whether components have failed.
Note 8: While pin leakage current may be used as a guide in determining the ESD withstand voltage, it is not an adequate criterion of component failure for complex integrated circuits.
Note 9: Static and dynamic testing
immediately following the ESD stressing provides worst-case test data results. With some components, static and dynamic
characteristics may be out of specified data sheet limits when tested immediately following ESD stressing, but drift towards acceptable levels with time. If static and dynamic testing is delayed, the component may be improperly classified at a higher ESD withstand voltage.
Note 10: If static and dynamic testing is to be performed at several temperatures, perform the tests first at the lowest
temperature, followed by the increasing temperatures in sequence.
9.2 CDM Component Classification Testing Procedure
Classify components according to their CDM ESD withstand voltage as shown in table 1. Stress test the components according to the
procedure below. Testing may be initiated at any level desired. If the component fails, continue testing at a lower voltage until the withstand voltage is found. If the component passes at the initial level, continue testing following the voltage levels specified in table 2 until the component fails or the maximum charge voltage is reached. CDM ESD classification testing shall be
considered destructive, even if the component does not fail during testing. Smaller voltage level increments may be used to determine withstand voltage if desired.
Note11: A change in component package, manufacturing processes, design, or materials may require
component reclassification according to this standard. Even if the same chip is used in a different package it should be requalified; no generic qualifications should be allowed.
ESD-STM5.3.1-1999
The following procedure shall be used to classify components:
9.2.1 Test a minimum of three samples of the
component to all specified static and dynamic data sheet parameters.
9.2.2 Install the first component and begin
testing using a stress level from table 2.
9.2.3 Raise the component potential using either
of the methods, as specified in section 5. Discharge the component through the pin under test. Apply a total of six discharges (three positive and three negative) to each pin. The time between discharges shall be sufficient to allow for the component to reach the full test voltage, with a minimum time between discharge pulses of one second.
Repeat for each pin to be tested.
9.2.4 Repeat steps 9.2.2 and 9.2.3 until all three
components have been tested. Record the stress level.
9.2.5 Test the components to all full static and
dynamic data sheet parameters and record the results for each component. Parametric and functional testing shall be performed at room temperature or as
specified in the component specification. If testing is required at multiple
temperatures, testing shall be performed first at the lowest temperature followed by the increasing temperatures in sequence first.
If all the components pass the specified
data sheet parameters, repeat steps 9.2.3 through 9.2.5, using the next higher stress level of table 2.
9.2.6 If one or more components fail, repeat the
ESD stress test using three new
components starting at the next lower
stress level. If the components continue to fail, decrease the stress voltage until level one is reached. If any additional failures are observed at level one, stop all testing at this level.
9.2.7 As an alternative, three new components
may be used at each stress level of table 2. Separate devices may also be used for each polarity and pin. Document and report the sample size and test plan.
10. Classification Criteria
The component classification is the highest ESD stress voltage level (both positive and negative polarities) at which a sample of at least three components has passed full static and dynamic data sheet parameters following ESD testing.
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ESD-STM5.3.1-1999
8.0Ip190% Ip16.0CURRENT (AMPERES)4.0Td2.010% Ip1Ip30.0Tr-2.0Ip2-4.00.00.51.01.52.0
TIME (NANOSECONDS)Figure 1: CDM ESD waveform for the verification modules, using a 3.5 gigahertz bandwidth measurement system
Requirements for the 3.5 gigahertz:
Charge voltage Volts ± 5%
125 250 500 1000 1500 2000
Symbol
Ip1 Ip1 Ip1 Ip1 Ip1 Ip1 Symbol tr (ps) td (ps) Ip2 Ip3
4 pF
Verification module Amperes ± 20%
1.9
3.75 7.5 15.0 22.5 30.00
4 pF Verification Module
All voltages <200 ps
<400 ps <50% Ip1 <25% Ip1
30 pF
Verification module Amperes ± 20%
18.00
30 pF Verification Module
500V only <250 ps
<700 ps <50% Ip1 <25% Ip1
Parameter Rise Time
Full width at Half Height
Max 2nd peak Max 3rd peak
Note 12: For the positive polarity: Ip2 is the second peak, the undershoot negative peak; Ip3 is the third peak, the overshoot positive peak. For the negative polarity: Ip2 is the second peak, the overshoot positive peak; Ip3 is the third peak, the undershoot positive peak.
Note 13: Caution; Many CDM testers use a coaxial 1 Ohm resistor probe to measure the current. In such set-up one measures the voltage across the coaxial resistor. This voltage read-out can be translated in a current read-out by dividing the voltage numbers by the resistor value of the coaxial resistor. Therefore it is important
to use the actual resistor value and not an assumed value of 1 Ohm. 8
ESD-STM5.3.1-1999
5.0Ip190% Ip14.03.0CURRENT (AMPERES)2.0Td1.010% Ip10.0Tr-1.0Ip20.00.5TIME (NANOSECONDS)1.0Ip3-2.01.52.0
Figure 2: CDM ESD waveform for the standard verification modules using the one gigahertz bandwidth measurement system
Requirements for one gigahertz:
Charge Voltage Volts ± 5%
125 250 500 1000 1500 2000
Symbol
Ip1 Ip1 Ip1 Ip1 Ip1 Ip1 Symbol tr (ps) td (ps) Ip2 Ip3
4 pF
Verification Module Amperes ± 20 %
1.13
2.25 4.50 9.00 13.50 18.00
4 pF Verification Module
All Voltages <400 ps
<600 ps <50% Ip1 <25% Ip1
30 pF
Verification Module Amperes ± 20%
14.00
30 pF Verification Module
500 V only <400 ps
<1000 ps <50% Ip1 <25% Ip1
Parameter Rise Time
Full width at Half Height
Max 2nd peak Max 3rd peak
Note 14: For the positive polarity: Ip2 is the second peak, the undershoot negative peak; Ip3 is the third peak, the overshoot positive peak. For the negative polarity: Ip2 is the second peak, the overshoot positive peak; Ip3 is the third peak, the undershoot positive peak.
Note 15: Caution; Many CDM testers use a coaxial 1 Ohm resistor probe to measure the current. In such set-up one measures the voltage across the coaxial resistor. This voltage read-out can be translated in a current read-out by dividing the voltage numbers by the resistor value of the coaxial resistor. Therefore it is important to use the actual resistor value and not an assumed value of 1 Ohm.
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ESD-STM5.3.1-1999
11. Appendix 1: Verification Modules for Non-Socketed Mode Testing
Figure 3: 30 pF verification module with 26 mm disk Figure 4: 4 pF verification module with 9 mm disk
Note 16: Material: FR-4 0.8 mm thick, minimum size 30 x 30 mm
Note 17: Gold or nickel plated etched copper disks centered on one side of the FR-4 material Note 18: 30 pF disk is approximately 26 mm diameter; 4 pF disk is approximately 9 mm diameter
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ESD-STM5.3.1-1999
12. Appendix 2: Discharge Test Method Guidance
12.1 Non-contact Mode Discharge
Air discharge attempts to simulate the CDM event as it would naturally occur in the environment. The discharge occurs across a small air gap. The actual discharge will vary depending upon a number of factors that are
difficult to control, such as air pressure, humidity and electrode shapes and cleanliness. These tend to alter the discharge characteristics, making replication in a test environment difficult. Some testers overcome the
humidity and pressure issues by creating a controlled local environment using a dry inert gas such as nitrogen. Frequent cleaning of the discharge electrode, and component pins before testing, can go a long way to
alleviating the contamination issues. A variation in peak current of up to 20% from discharge to discharge is reasonable for non-contact mode discharges.
The major advantages of the non-contact mode discharge technique are that it truly represents the natural discharge conditions, and minimizes the parasitic circuit elements.
The major disadvantages are an inability to ensure discharges to a chosen pin when testing devices with very close pin spacing, and difficulty in reproducing discharge events within close tolerances.
12.2 Contact Mode Discharge
The contact mode simulates the ESD event in a way that is repeatable. However, the actual current waveforms obtained are different from the non-contact mode waveforms, and are more representative of the circuit
parasitics than the device. The major disadvantages of contact mode testing are the additional capacitance and additional inductance in the discharge path, which largely determine the current waveform.
A major advantage of contact mode testing is the repeatability of the test on a given tester, and the ability to more easily test devices with a fine lead pitch.
The major disadvantage of contact mode testing is that parasitics significantly influence the discharge current waveform.
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ESD-STM5.3.1-1999
13. Appendix 3: Recommended Component, Verification Module and Tester Cleaning Method
To avoid charge loss in verification modules during CDM evaluation, the verification modules should be
cleaned with isopropanol using a procedure approved by the local safety organization. Components should then be handled only by vacuum tweezers, personnel wearing finger cots or equivalent, or plastic tweezers which have been neutralized by holding in an ionized air stream.
The tester should be cleaned periodically with isopropanol (isopropyl alcohol) to remove any surface contamination that could result in charge loss. Particular attention should be paid to the discharge probe, charging probe and the ground plane on which the device is placed.
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