FLIP-FLOP CIRCUIT

专利名称：FLIP-FLOP CIRCUIT发明人：YAMAKAWA SHIGEKI申请号：JP23572185申请日：19851021公开号：JPS6295019A公开日：19870501

摘要：PURPOSE:To prevent the generation of a malfunction without requiring achange of a gate length and a gate width of a transistor, by providing two pieces ofcomposite logic circuits. CONSTITUTION:The first composite logic circuit 23 in which thefirst plural OR input terminals are connected to a reset signal input terminal IN3, and thesecond composite logic circuit 24 in which an output terminal is connected to the seconddata output terminal OUT2 are provided. When a reset signal 03 is a low level, it is reset,but the reset signal 03 is supplied to all input terminals of a multi-input OR circuit of thecomposite logic circuits 23, 24. By replacing an input terminal to which a reset signal of atwo-input NAND circuit for receiving said reset signal has been inputted, with the multi-input OR circuit, and also supplying the reset signal to all input terminals of the multi-input OR circuit, a logical threshold voltage in the reset signal input terminal can bedropped without changing a gate length and a gate width of a transistor.

申请人：NEC CORP

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