专利名称：Flip-flop circuit
发明人：Kinugasa, Masanori, c/o Int. Property
Division,Ishikawa, Toshimasa, c/o Int.Property Division,Kida, Munenobu, c/o Int.Property Division
申请号：EP90117070.4申请日：19900905公开号：EP0416576A3公开日：19920401
专利附图：
摘要：In a master-slave type flip-flop circuit comprising a master output holding
circuit (13) of the master stage circuit, the threshold value of the input circuit of the slavestage circuit (17) has a hysteresis characteristic in which the high level threshold value (V)is set to a higher value than the threshold value of the master output holding circuit andthe low level threshold value (V) is set to a lower value than the threshold value of themaster output holding circuit. Due to the feature, a phenomenon is prevented in whichthe output is once inverted and then again inverted in the metastable state.
申请人：KABUSHIKI KAISHA TOSHIBA,TOSHIBA MICRO-ELECTRONICS CORPORATION
地址：72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 JP,25-1,Ekimaehoncho Kawasaki-ku, Kawasaki-shi JP
国籍：JP,JP
代理机构：Lehn, Werner, Dipl.-Ing.
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