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CC2500CC2500Low-CostLow-Power2.4GHzRFTransceiver

Applications

2400-2483.5MHzISM/SRDbandsystemsConsumerelectronicsWirelessgamecontrollers

Wirelessaudio

WirelesskeyboardandmouseRFenabledremotecontrols

ProductDescription

TheCC2500isalow-cost2.4GHztransceiverdesignedforverylow-powerwirelessappli-cations.Thecircuitisintendedforthe2400-2483.5MHzISM(Industrial,ScientificandMedical)andSRD(ShortRangeDevice)frequencyband.

TheRFtransceiverisintegratedwithahighlyconfigurablebasebandmodem.Themodemsupportsvariousmodulationformatsandhasaconfigurabledatarateupto500kBaud.

controlledviaanSPIinterface.Inatypicalsystem,theCC2500willbeusedtogetherwithamicrocontrollerandafewadditionalpassivecomponents.

201918179CC2500providesextensivehardwaresupportforpackethandling,databuffering,bursttransmissions,clearchannelassessment,linkqualityindication,andwake-on-radio.

Themainoperatingparametersandthe-bytetransmit/receiveFIFOsofCC2500canbe





limit)

Programmableoutputpowerupto+1dBmExcellentreceiverselectivityandblockingperformance

Programmabledataratefrom1.2to500kBaud

Frequencyrange:2400–2483.5MHz



frequencysynthesizerwith90ussettlingtime

AutomaticFrequencyCompensation(AFC)canbeusedtoalignthefrequencysynthesizertothereceivedcentrefrequency

Integratedanalogtemperaturesensor

DigitalFeatures



Flexiblesupportforpacketorientedsystems:On-chipsupportforsyncworddetection,addresscheck,flexiblepacketlength,andautomaticCRChandling

EfficientSPIinterface:Allregisterscanbeprogrammedwithone“burst”transferDigitalRSSIoutput

ProgrammablechannelfilterbandwidthProgrammableCarrierSense(CS)indicator

Page1of

AnalogFeatures



OOK,2-FSK,GFSK,andMSKsupportedSuitableforfrequencyhoppingandmulti-channelsystemsduetoafastsettling



SWRS040C

1067816CC2500ProgrammablePreambleQualityIndicatorGeneral

(PQI)forimprovedprotectionagainstfalsesyncworddetectioninrandomnoise

SupportforautomaticClearChannelAssessment(CCA)beforetransmitting(forlisten-before-talksystems)

Supportforper-packageLinkQualityIndication(LQI)



Optionalautomaticwhiteningandde-whiteningofdata



Low-PowerFeatures

400nASLEEPmodecurrentconsumption

Faststartuptime:240usfromSLEEPtoRXorTXmode(measuredonEMdesign)Wake-on-radiofunctionalityforautomaticlow-powerRXpolling



Separate-byteRXandTXdataFIFOs(enablesburstmodedatatransmission)

SWRS040CFewexternalcomponents:Completeon-chipfrequencysynthesizer,noexternalfiltersorRFswitchneeded

Greenpackage:RoHScompliantandnoantimonyorbromine

Smallsize(QLP4x4mmpackage,20pins)

SuitedforsystemscompliantwithEN300328andEN300440class2(Europe),FCCCFR47Part15(US),andARIBSTD-T66(Japan)Supportforasynchronousandsynchronousserialreceive/transmitmodeforbackwardscompatibilitywithexistingradiocommunicationprotocols

Page2of

CC2500Abbreviations

Abbreviationsusedinthisdatasheetaredescribedbelow.

ACPADCAFCAGCAMRARIBAdjacentChannelPowerAnalogtoDigitalConverter

AutomaticFrequencyOffsetCompensationAutomaticGainControlAutomaticMeterReading

AssociationofRadioIndustriesandBusinessesMSBMSKNANRZOOKPAMostSignificantBitMinimumShiftKeyingNotApplicable

NonReturntoZero(Coding)OnOffKeyingPowerAmplifier

BERBitErrorRate

BTBandwidth-TimeproductCCAClearChannelAssessmentCFRCodeofFederalRegulationsCRCCyclicRedundancyCheckCSCarrierSense

CWContinuousWave(UnmodulatedCarrier)DCDirectCurrent

DVGADigitalVariableGainAmplifierESREquivalentSeriesResistance

FCCFederalCommunicationsCommissionFECForwardErrorCorrectionFIFOFirst-In-First-Out

FHSSFrequencyHoppingSpreadSpectrum2-FSKFrequencyShiftKeying

GFSKGaussianshapedFrequencyShiftKeyingIFIntermediateFrequencyI/QIn-Phase/Quadrature

ISMIndustrial,ScientificandMedicalLBTListenBeforeTransmitLCInductor-CapacitorLNALowNoiseAmplifierLOLocalOscillator

LQILinkQualityIndicatorLSBLeastSignificantBitMCU

MicrocontrollerUnit

PCBPDPERPLLPORPQIPQTRCOSCQPSKQLPRCRFRSSIRXSMDSNRSPISRDT/RTXVCOWLANWORXOSCXTAL

SWRS040CPrintedCircuitBoardPowerDown

PacketErrorRatePhaseLockedLoopPower-onReset

PreambleQualityIndicatorPreambleQualityThresholdRCOscillator

QuadraturePhaseShiftKeyingQuadLeadlessPackageResistor-CapacitorRadioFrequency

ReceivedSignalStrengthIndicatorReceive,ReceiveModeSurfaceMountDeviceSignaltoNoiseRatio

SerialPeripheralInterfaceShortRangeDeviceTransmit/Receive

Transmit,TransmitModeVoltageControlledOscillatorWirelessLocalAreaNetworks

WakeonRadio,LowpowerpollingCrystalOscillatorCrystal

Page3of

CC2500TableofContents

APPLICATIONS...........................................................................................................................................1PRODUCTDESCRIPTION.........................................................................................................................1KEYFEATURES..........................................................................................................................................1RFPERFORMANCE...........................................................................................................................................1ANALOGFEATURES..........................................................................................................................................1DIGITALFEATURES..........................................................................................................................................1LOW-POWERFEATURES...................................................................................................................................2GENERAL..........................................................................................................................................................2ABBREVIATIONS........................................................................................................................................3TABLEOFCONTENTS..............................................................................................................................41ABSOLUTEMAXIMUMRATINGS...........................................................................................................62OPERATINGCONDITIONS......................................................................................................................63GENERALCHARACTERISTICS...............................................................................................................ELECTRICALSPECIFICATIONS...............................................................................................................74.1CURRENTCONSUMPTION.....................................................................................................................74.2RFRECEIVESECTION...........................................................................................................................94.3RFTRANSMITSECTION......................................................................................................................114.4CRYSTALOSCILLATOR.......................................................................................................................124.5LOWPOWERRCOSCILLATOR............................................................................................................124.6FREQUENCYSYNTHESIZERCHARACTERISTICS...................................................................................134.7ANALOGTEMPERATURESENSOR.......................................................................................................144.8DCCHARACTERISTICS.......................................................................................................................144.9POWER-ONRESET..............................................................................................................................145PINCONFIGURATION..........................................................................................................................156CIRCUITDESCRIPTION........................................................................................................................177APPLICATIONCIRCUIT........................................................................................................................178CONFIGURATIONOVERVIEW..............................................................................................................199CONFIGURATIONSOFTWARE..............................................................................................................20104-WIRESERIALCONFIGURATIONANDDATAINTERFACE...................................................................2110.1CHIPSTATUSBYTE............................................................................................................................2210.2REGISTERACCESS..............................................................................................................................2310.3SPIREAD...........................................................................................................................................2310.4COMMANDSTROBES..........................................................................................................................2410.5FIFOACCESS.....................................................................................................................................2410.6PATABLEACCESS.............................................................................................................................2411MICROCONTROLLERINTERFACEANDPINCONFIGURATION...............................................................2511.1CONFIGURATIONINTERFACE..............................................................................................................2511.2GENERALCONTROLANDSTATUSPINS..............................................................................................2511.3OPTIONALRADIOCONTROLFEATURE...............................................................................................2612DATARATEPROGRAMMING...............................................................................................................2613RECEIVERCHANNELFILTERBANDWIDTH..........................................................................................2714DEMODULATOR,SYMBOLSYNCHRONIZERANDDATADECISION.......................................................2714.1FREQUENCYOFFSETCOMPENSATION.................................................................................................2714.2BITSYNCHRONIZATION......................................................................................................................2714.3BYTESYNCHRONIZATION...................................................................................................................2815PACKETHANDLINGHARDWARESUPPORT.........................................................................................2815.1DATAWHITENING..............................................................................................................................2915.2PACKETFORMAT................................................................................................................................2915.3PACKETFILTERINGINRECEIVEMODE...............................................................................................3115.4CRCCHECK.......................................................................................................................................3115.5PACKETHANDLINGINTRANSMITMODE............................................................................................3215.6PACKETHANDLINGINRECEIVEMODE..............................................................................................3215.7PACKETHANDLINGINFIRMWARE......................................................................................................3316MODULATIONFORMATS.....................................................................................................................3316.1FREQUENCYSHIFTKEYING................................................................................................................3316.2MINIMUMSHIFTKEYING....................................................................................................................33

SWRS040C

Page4of

CC250016.31717.117.217.317.417.517.61818.118.21919.119.219.319.419.519.619.720212222.12324252626.12728293030.130.23131.131.231.331.431.531.631.731.831.931.103232.132.232.33333.133.234353636.1

AMPLITUDEMODULATION.................................................................................................................34RECEIVEDSIGNALQUALIFIERSANDLINKQUALITYINFORMATION...................................................34SYNCWORDQUALIFIER.....................................................................................................................34PREAMBLEQUALITYTHRESHOLD(PQT)...........................................................................................34RSSI...................................................................................................................................................34CARRIERSENSE(CS)..........................................................................................................................35CLEARCHANNELASSESSMENT(CCA)..............................................................................................37LINKQUALITYINDICATOR(LQI).......................................................................................................37FORWARDERRORCORRECTIONWITHINTERLEAVING........................................................................37FORWARDERRORCORRECTION(FEC)...............................................................................................37INTERLEAVING...................................................................................................................................37RADIOCONTROL................................................................................................................................39POWER-ONSTART-UPSEQUENCE......................................................................................................39CRYSTALCONTROL............................................................................................................................40VOLTAGEREGULATORCONTROL.......................................................................................................40ACTIVEMODES..................................................................................................................................41WAKEONRADIO(WOR)...................................................................................................................41TIMING...............................................................................................................................................42RXTERMINATIONTIMER...................................................................................................................43DATAFIFO........................................................................................................................................43FREQUENCYPROGRAMMING..............................................................................................................44VCO...................................................................................................................................................45VCOANDPLLSELF-CALIBRATION...................................................................................................45VOLTAGEREGULATORS.....................................................................................................................46OUTPUTPOWERPROGRAMMING........................................................................................................46SELECTIVITY......................................................................................................................................48CRYSTALOSCILLATOR.......................................................................................................................50REFERENCESIGNAL...........................................................................................................................50EXTERNALRFMATCH.......................................................................................................................50PCBLAYOUTRECOMMENDATIONS....................................................................................................51GENERALPURPOSE/TESTOUTPUTCONTROLPINS...........................................................................52ASYNCHRONOUSANDSYNCHRONOUSSERIALOPERATION................................................................ASYNCHRONOUSOPERATION.............................................................................................................SYNCHRONOUSSERIALOPERATION...................................................................................................SYSTEMCONSIDERATIONSANDGUIDELINES.....................................................................................SRDREGULATIONS............................................................................................................................FREQUENCYHOPPINGANDMULTI-CHANNELSYSTEMS.....................................................................55WIDEBANDMODULATIONNOTUSINGSPREADSPECTRUM................................................................55DATABURSTTRANSMISSIONS............................................................................................................55CONTINUOUSTRANSMISSIONS...........................................................................................................55CRYSTALDRIFTCOMPENSATION.......................................................................................................56SPECTRUMEFFICIENTMODULATION..................................................................................................56LOWCOSTSYSTEMS..........................................................................................................................56BATTERYOPERATEDSYSTEMS..........................................................................................................56INCREASINGOUTPUTPOWER.........................................................................................................56CONFIGURATIONREGISTERS..............................................................................................................57CONFIGURATIONREGISTERDETAILS–REGISTERSWITHPRESERVEDVALUESINSLEEPSTATE......61CONFIGURATIONREGISTERDETAILS–REGISTERSTHATLOSEPROGRAMMINGINSLEEPSTATE.....80STATUSREGISTERDETAILS................................................................................................................81PACKAGEDESCRIPTION(QFN20).....................................................................................................85RECOMMENDEDPCBLAYOUTFORPACKAGE(QFN20)....................................................................85SOLDERINGINFORMATION.................................................................................................................85ORDERINGINFORMATION...................................................................................................................86REFERENCES.......................................................................................................................................86GENERALINFORMATION....................................................................................................................88DOCUMENTHISTORY.........................................................................................................................88

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CC25001

AbsoluteMaximumRatings

UndernocircumstancesmusttheabsolutemaximumratingsgiveninTable1beviolated.Stressexceedingoneormoreofthelimitingvaluesmaycausepermanentdamagetothedevice.

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CC25004

4.1

ElectricalSpecifications

CurrentConsumption

Tc=25C,VDD=3.0Vifnothingelsestated.AllmeasurementresultsobtainedusingtheCC2500EMreferencedesign([4]).Parameter

Currentconsumptioninpowerdownmodes

Min

Typ40090092160

Currentconsumption

8.1

Max

UnitnAnAAAA

Condition/Note

Voltageregulatortodigitalpartoff,registervaluesretained(SLEEPstate).AllGDOpinsprogrammedto0x2F(HWto0)Voltageregulatortodigitalpartoff,registervaluesretained,low-powerRCoscillatorrunning(SLEEPstatewithWORenabled)Voltageregulatortodigitalpartoff,registervaluesretained,XOSCrunning(SLEEPstatewithMCSM0.OSC_FORCE_ONset)Voltageregulatortodigitalparton,allothermodulesinpowerdown(XOFFstate)

AutomaticRXpollingonceeachsecond,usinglow-powerRCoscillator,with460kHzfilterbandwidthand250kBauddatarate,PLLcalibrationevery4thwakeup.Averagecurrentwithsignalinchannelbelowcarriersenselevel(MCSM2.RX_TIME_RSSI=1).Sameasabove,butwithsignalinchannelabovecarriersenselevel,1.95msRXtimeout,andnopreamble/syncwordfound.AutomaticRXpollingevery15thsecond,usinglow-powerRCoscillator,with460kHzfilterbandwidthand250kBauddatarate,PLLcalibrationevery4thwakeup.Averagecurrentwithsignalinchannelbelowcarriersenselevel(MCSM2.RX_TIME_RSSI=1).Sameasabove,butwithsignalinchannelabovecarriersenselevel,29.3msRXtimeout,andnopreamble/syncwordfound.Onlyvoltageregulatortodigitalpartandcrystaloscillatorrunning(IDLEstate)

Onlythefrequencysynthesizerisrunning(FSTXONstate).Thiscurrentconsumptionisalsorepresentativefortheother

intermediatestateswhengoingfromIDLEtoRXorTX,includingthecalibrationstate.

Receivemode,2.4kBaud,inputatsensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=0

Receivemode,2.4kBaud,inputwellabovesensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=0

Receivemode,10kBaud,inputatsensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=0

Receivemode,10kBaud,inputwellabovesensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=0

Receivemode,250kBaud,inputatsensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=0

Receivemode,250kBaud,inputwellabovesensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=0

Receivemode,250kBaudcurrentoptimized,inputatsensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=1

Receivemode,250kBaudcurrentoptimized,inputwellabovesensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=1Receivemode,500kBaud,inputatsensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=0

Receivemode,500kBaud,inputwellabovesensitivitylimit,MDMCFG2.DEM_DCFILT_OFF=0

351.4

AA

341.57.4

AmAmA

Currentconsumption,RXstates

17.014.517.314.918.815.716.613.319.617.0

mAmAmAmAmAmAmAmAmAmA

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CC2500Currentconsumption,TXstates

11.115.021.221.5

mAmAmAmA

Transmitmode,–12dBmoutputpowerTransmitmode,-6dBmoutputpowerTransmitmode,0dBmoutputpowerTransmitmode,+1dBmoutputpower

Table4:CurrentConsumption

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CC25004.2

RFReceiveSection

Tc=25C,VDD=3.0Vifnothingelsestated.AllmeasurementresultsobtainedusingtheCC2500EMreferencedesign([4]).ParameterDigitalchannelfilterbandwidth

Min58

Typ

Max812

UnitkHz

Condition/Note

Userprogrammable.Thebandwidthlimitsare

proportionaltocrystalfrequency(givenvaluesassumea26.0MHzcrystal).

2.4kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0

(2-FSK,1%packeterrorrate,20bytespacketlength,203kHzdigitalchannelfilterbandwidth)Receiversensitivity

–104

dBm

TheRXcurrentconsumptioncanbereducedbyapproximately1.7mAbysetting

MDMCFG2.DEM_DCFILT_OFF=1.Thetypicalsensitivityisthen-102dBmandthetemperaturerangeisfrom0oCto+85oC.

Thesensitivitycanbeimprovedtotypically–106dBmwithMDMCFG2.DEM_DCFILT_OFF=0byprogrammingregistersTEST2andTEST1(seepage82).Thetemperaturerangeisthenfrom0oCto+85oC.

SaturationAdjacentchannelrejectionAlternatechannelrejection

–132331

dBmdBdB

Desiredchannel3dBabovethesensitivitylimit.250kHzchannelspacing

SeeFigure22forplotofselectivityversusfrequencyoffset

Blocking±10MHzoffset±20MHzoffset±50MHzoffset

7071

dBmdBmdBm

Wantedsignal3dBabovesensitivitylevel.CompliantwithETSIEN300440class2receiverrequirements.

10kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0

(2-FSK,1%packeterrorrate,20bytespacketlength,232kHzdigitalchannelfilterbandwidth)Receiversensitivity

–99

dBm

TheRXcurrentconsumptioncanbereducedbyapproximately1.7mAbysetting

MDMCFG2.DEM_DCFILT_OFF=1.Thetypicalsensitivityisthen-97dBm

Thesensitivitycanbeimprovedtotypically–101dBmwithMDMCFG2.DEM_DCFILT_OFF=0byprogrammingregistersTEST2andTEST1(seepage82).Thetemperaturerangeisthenfrom0oCto+85oC.

SaturationAdjacentchannelrejectionAlternatechannelrejection

–91825

dBmdBdB

Desiredchannel3dBabovethesensitivitylimit.250kHzchannelspacing

SeeFigure23forplotofselectivityversusfrequencyoffset

Blocking±10MHzoffset±20MHzoffset±50MHzoffset

596566

dBdBdB

Wantedsignal3dBabovesensitivitylevel.CompliantwithETSIEN300440class2receiverrequirements.

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CC2500Parameter

Min

Typ

Max

Unit

Condition/Note

250kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0

(MSK,1%packeterrorrate,20bytespacketlength,0kHzdigitalchannelfilterbandwidth)ReceiversensitivitySaturation

AdjacentchannelrejectionAlternatechannelrejection

––132130

dBmdBmdBdB

Desiredchannel3dBabovethesensitivitylimit.750kHzchannelspacing

SeeFigure24forplotofselectivityversusfrequencyoffset

Blocking±10MHzoffset±20MHzoffset±50MHzoffset

465355

dBdBdB

Wantedsignal3dBabovesensitivitylevel.CompliantwithETSIEN300440class2receiverrequirements.

250kBauddatarate,currentoptimized,MDMCFG2.DEM_DCFILT_OFF=1

(MSK,1%packeterrorrate,20bytespacketlength,0kHzdigitalchannelfilterbandwidth)ReceiversensitivitySaturation

AdjacentchannelrejectionAlternatechannelrejection

–87–122130

dBmdBmdBdB

Desiredchannel3dBabovethesensitivitylimit.750kHzchannelspacing

SeeFigure25forplotofselectivityversusfrequencyoffset

Blocking±10MHzoffset±20MHzoffset±50MHzoffset

465255

dBdBdB

Wantedsignal3dBabovesensitivitylevel.CompliantwithETSIEN300440class2receiverrequirements.

500kBauddatarate,MDMCFG2.DEM_DCFILT_OFF=0(MDMCFG2.DEM_DCFILT_OFF=1cannotbeusedfordatarates>250kBaud)

(MSK,1%packeterrorrate,20bytespacketlength,812kHzdigitalchannelfilterbandwidth)ReceiversensitivitySaturation

AdjacentchannelrejectionAlternatechannelrejection

–83–181425

dBmdBmdBdB

Desiredchannel3dBabovethesensitivitylimit.1MHzchannelspacing

SeeFigure26forplotofselectivityversusfrequencyoffset

Blocking±10MHzoffset±20MHzoffset±50MHzoffsetGeneral

Spuriousemissions25MHz–1GHzAbove1GHzRXlatency

–57–47

dBmdBmbit

Serialoperation.Timefromstartofreceptionuntildataisavailableonthereceiverdataoutputpinisequalto9bit.

404850

dBdBdB

Wantedsignal3dBabovesensitivitylevel.CompliantwithETSIEN300440class2receiverrequirements.

Table5:RFReceiveSection

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CC25004.3

RFTransmitSection

Tc=25C,VDD=3.0V,0dBmifnothingelsestated.AllmeasurementresultsobtainedusingtheCC2500EMreferencedesign([4]).ParameterDifferentialloadimpedanceOutputpower,highestsetting

Min

Typ80+j74

Max

Unit

Condition/Note

DifferentialimpedanceasseenfromtheRF-port(RF_PandRF_N)towardstheantenna.FollowtheCC2500EMreferencedesign([4])availablefromtheTIwebsite.Outputpowerisprogrammableandfullrangeisavailableacrosstheentirefrequencyband.

Deliveredtoa50single-endedloadviaCC2500EMreferencedesign([4])RFmatchingnetwork.

Outputpower,lowestsetting

–30

dBm

Outputpowerisprogrammableandfullrangeisavailableacrosstheentirefrequencyband.

Deliveredtoa50single-endedloadviaCC2500EMreferencedesign([4])RFmatchingnetwork.

Itispossibletoprogramlessthan-30dBmoutputpower,butthisisnotrecommendedduetolargevariationinoutputpoweracrossoperatingconditionsandprocessingcornersforthesesettings.

Occupiedbandwidth(99%)

9111729

Adjacentchannelpower(ACP)

-28-27-22-21

Spuriousemissions25MHz–1GHz47-74,87.5-118,174-230,470-862MHz1800-1900MHzAt2∙RFand3∙RFOtherwiseabove1GHzTXlatency

–36––47–41–30

dBmdBmdBmdBmdBmbit

Serialoperation.TimefromsamplingthedataonthetransmitterdatainputpinuntilitisobservedontheRFoutputports.

RestrictedbandinEuropeRestrictedbandsinUSA

kHzkHzkHzkHzdBcdBcdBcdBc

2.4kBaud,38.2kHzdeviation,2-FSK10kBaud,38.2kHzdeviation,2-FSK250kBaud,MSK500kBaud,MSK

2.4kBaud,38.2kHzdeviation,2-FSK,250kHzchannelspacing

10kBaud,38.2kHzdeviation,2-FSK,250kHzchannelspacing

250kBaud,MSK,750kHzchannelspacing500kBaud,MSK,1MHzchannelspacing

+1dBm

Table6:RFTransmitSection

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CC25004.4

CrystalOscillator

Tc=25C,VDD=3.0Vifnothingelsestated.ParameterCrystalfrequencyTolerance

Min26

Typ26±40

Max27

UnitMHzppm

Thisisthetotaltoleranceincludinga)initialtolerance,b)crystalloading,c)aging,andd)temperaturedependence.

TheacceptablecrystaltolerancedependsonRFfrequencyandchannelspacing/bandwidth.

ESRStart-uptime

150

100

µs

MeasuredonCC2500EMreferencedesign([4])usingcrystalAT-41CD2fromNDK.

Thisparameteristoalargedegreecrystaldependent.Condition/Note

Table7:CrystalOscillatorParameters

4.5

LowPowerRCOscillator

Tc=25C,VDD=3.0Vifnothingelsestated.AllmeasurementresultsobtainedusingtheCC2500EMreferencedesign([4]).Parameter

CalibratedfrequencyFrequencyaccuracyaftercalibration

Min34.7

Typ34.7

Max36-1/+10

UnitkHz%

Condition/Note

CalibratedRCoscillatorfrequencyisXTALfrequencydividedby750

TheRCoscillatorcontainsanerrorinthecalibrationroutinethatstatisticallyoccursin17.3%ofallcalibrationsperformed.Thegivenmaximumaccuracyfiguresaccountforthecalibrationerror.ReferalsototheCC2500ErrataNotes.

Frequencydriftwhentemperaturechangesaftercalibration

Frequencydriftwhensupplyvoltagechangesaftercalibration

WhentheRCoscillatorisenabled,calibrationiscontinuouslydoneinthebackgroundaslongasthecrystaloscillatorisrunning.

TemperaturecoefficientSupplyvoltagecoefficientInitialcalibrationtime

+0.4+32

%/C%/Vms

Table8:RCOscillatorParameters

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CC25004.6

FrequencySynthesizerCharacteristics

Tc=25C,VDD=3.0Vifnothingelsestated.AllmeasurementresultsobtainedusingtheCC2500EMreferencedesign([4]).Minfiguresaregivenusinga27MHzcrystal.Typandmaxfiguresaregivenusinga26MHzcrystal.Parameter

Programmed

frequencyresolutionSynthesizerfrequencytolerance

RFcarrierphasenoise

Min397

TypFXOSC/216±40

Max412

UnitHzppm

Condition/Note26-27MHzcrystal.

Givenbycrystalused.Requiredaccuracy(including

temperatureandaging)dependsonfrequencybandandchannelbandwidth/spacing.@50kHzoffsetfromcarrier@100kHzoffsetfromcarrier@200kHzoffsetfromcarrier@500kHzoffsetfromcarrier@1MHzoffsetfromcarrier@2MHzoffsetfromcarrier@5MHzoffsetfromcarrier@10MHzoffsetfromcarrier

TimefromleavingtheIDLEstateuntilarrivingintheRX,FSTXONorTXstate,whennotperformingcalibration.Crystaloscillatorrunning.

Settlingtimeforthe1·IFfrequencystepfromRXtoTXSettlingtimeforthe1·IFfrequencystepfromTXtoRXCalibrationcanbeinitiatedmanuallyorautomaticallybeforeenteringorafterleavingRX/TX.

–78–78–81–90–100–108–114–118

dBc/HzdBc/HzdBc/HzdBc/HzdBc/HzdBc/HzdBc/HzdBc/Hz

88.4

s

PLLturn-on/hoptime85.188.4

PLLRX/TXsettlingtime

PLLTX/RXsettlingtime

PLLcalibrationtime

9.320.7694

9.621.5721

sss

Table9:FrequencySynthesizerParameters

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CC25004.7

AnalogTemperatureSensor

Thecharacteristicsoftheanalogtemperaturesensorat3.0VsupplyvoltagearelistedinTable10below.Notethatitisnecessarytowrite0xBFtothePTESTregistertousetheanalogtemperaturesensorintheIDLEstate.

Parameter

Outputvoltageat–40COutputvoltageat0COutputvoltageat+40COutputvoltageat+80CTemperaturecoefficientErrorincalculated

temperature,calibrated

-2*Min

Typ0.60.7500.8480.9462.430

2*Max

UnitVVVVmV/CC

Fittedfrom–20Cto+80C

From–20Cto+80Cwhenusing2.43mV/C,after1-pointcalibrationatroomtemperature

Condition/Note

Theindicatedminimumandmaximumerrorwith1-pointcalibrationisbasedonmeasuredvaluesfortypicalprocessparameters

Currentconsumptionincreasewhenenabled

0.3

Table10:AnalogTemperatureSensorParameters

4.8

DCCharacteristics

Tc=25Cifnothingelsestated.DigitalInputs/OutputsLogic\"0\"inputvoltageLogic\"1\"inputvoltageLogic\"0\"outputvoltageLogic\"1\"outputvoltageLogic\"0\"inputcurrentLogic\"1\"inputcurrent

Min0VDD-0.7

0VDD-0.3N/AN/A

Max0.7VDD0.5VDD–5050

UnitVVVVnAnA

Forupto4mAoutputcurrentForupto4mAoutputcurrentInputequals0VInputequalsVDDCondition/Note

Table11:DCCharacteristics

4.9

Power-OnReset

WhenthepowersupplycomplieswiththerequirementsinTable12below,properPower-On-Resetfunctionalityisguaranteed.Otherwise,thechipshouldbeassumedtohaveunknownstateuntiltransmittinganSRESstrobeovertheSPIinterface.SeeSection19.1onpage39forfurtherdetails.

Parameter

Powerramp-uptimePowerofftime

1Min

Typ

Max5

Unitmsms

Condition/Note

From0Vuntilreaching1.8V

Minimumtimebetweenpower-onandpower-off

Table12:Power-onResetRequirements

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CC25005

PinConfiguration

DGUARDRBIASGND2019181716SCLK1SO(GDO1)2

GDO23DVDD4DCOUPL5

6GDO0(ATEST)7CSn8XOSC_Q1910AVDDXOSC_Q215AVDD14AVDD13RF_N12RF_P11AVDDGNDExposeddieattachpad

Figure1:PinoutTopView

Note:Theexposeddieattachpadmustbeconnectedtoasolidgroundplaneasthisisthemaingroundconnectionforthechip.

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CC2500Pin#12

PinNameSCLKSO(GDO1)

PinTypeDigitalInputDigitalOutput

Description

Serialconfigurationinterface,clockinputSerialconfigurationinterface,dataoutput.OptionalgeneraloutputpinwhenCSnishigh

GDO2

DigitalOutput

Digitaloutputpinforgeneraluse:TestsignalsFIFOstatussignalsClearChannelIndicator

Clockoutput,down-dividedfromXOSCSerialoutputRXdata

DVDDDCOUPL

Power(Digital)Power(Digital)

1.8-3.6VdigitalpowersupplyfordigitalI/O’sandforthedigitalcorevoltageregulator

1.6-2.0Vdigitalpowersupplyoutputfordecoupling.

NOTE:ThispinisintendedforusewiththeCC2500only.Itcannotbeusedtoprovidesupplyvoltagetootherdevices.

GDO0(ATEST)

DigitalI/O

Digitaloutputpinforgeneraluse:TestsignalsFIFOstatussignalsClearChannelIndicator

Clockoutput,down-dividedfromXOSCSerialoutputRXdataSerialinputTXdata

AlsousedasanalogtestI/Oforprototype/productiontesting

7101112

CSnXOSC_Q1AVDDXOSC_Q2AVDDRF_P

DigitalInputAnalogI/OPower(Analog)AnalogI/OPower(Analog)RFI/O

Serialconfigurationinterface,chipselectCrystaloscillatorpin1,orexternalclockinput1.8-3.6VanalogpowersupplyconnectionCrystaloscillatorpin2

1.8-3.6VanalogpowersupplyconnectionPositiveRFinputsignaltoLNAinreceivemodePositiveRFoutputsignalfromPAintransmitmode

RF_N

RFI/O

NegativeRFinputsignaltoLNAinreceivemodeNegativeRFoutputsignalfromPAintransmitmode

14151617181920

AVDDAVDDGNDRBIASDGUARDGNDSI

Power(Analog)Power(Analog)Ground(Analog)AnalogI/OPower(Digital)Ground(Digital)DigitalInput

1.8-3.6Vanalogpowersupplyconnection1.8-3.6VanalogpowersupplyconnectionAnaloggroundconnection

ExternalbiasresistorforreferencecurrentPowersupplyconnectionfordigitalnoiseisolationGroundconnectionfordigitalnoiseisolationSerialconfigurationinterface,datainput

Table13:PinoutOverview

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CC25006

CircuitDescription

RADIOCONTROLDEMODULATORPACKETHANDLERADCRF_PRF_N

DIGITALINTERFACETOMCULNAFEC/INTERLEAVERRXFIFOADCSCLKSO(GDO1)SICSn

GDO0(ATEST)GDO2

090FREQSYNTHRCOSCBIASXOSCRBIASXOSC_Q1XOSC_Q2

Figure2:CC2500SimplifiedBlockDiagram

signalstothedown-conversionmixersinreceivemode.

AcrystalistobeconnectedtoXOSC_Q1andXOSC_Q2.Thecrystaloscillatorgeneratesthereferencefrequencyforthesynthesizer,aswellasclocksfortheADCandthedigitalpart.A4-wireSPIserialinterfaceisusedforconfigurationanddatabufferaccess.

Thedigitalbasebandincludessupportforchannelconfiguration,packethandling,anddatabuffering.

AsimplifiedblockdiagramofCC2500isshowninFigure2.

CC2500featuresalow-IFreceiver.ThereceivedRFsignalisamplifiedbythelow-noiseamplifier(LNA)anddown-convertedinquadrature(IandQ)totheintermediatefrequency(IF).AtIF,theI/QsignalsaredigitisedbytheADCs.Automaticgaincontrol(AGC),finechannelfiltering,demodulationbit/packetsynchronizationareperformeddigitally.

ThetransmitterpartofCC2500isbasedondirectsynthesisoftheRFfrequency.

Thefrequencysynthesizerincludesacompletelyon-chipLCVCOanda90degreesphaseshifterforgeneratingtheIandQLO

7ApplicationCircuit

BiasResistor

ThebiasresistorR171isusedtosetanaccuratebiascurrent.BalunandRFMatching

ThecomponentsbetweentheRF_N/RF_Ppinsandthepointwherethetwosignalsarejoinedtogether(C122,C132,L121,andL131)forma

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Page17of

OnlyafewexternalcomponentsarerequiredforusingtheCC2500.TherecommendedapplicationcircuitisshowninFigure3.TheexternalcomponentsaredescribedinTable14,andtypicalvaluesaregiveninTable15.

TXFIFOPAMODULATORCC2500balunthatconvertsthedifferentialRFsignalonCC2500toasingle-endedRFsignal.C121andC131areneededforDCblocking.TogetherwithanappropriateLCnetwork,thebaluncomponentsalsotransformtheimpedancetomatcha50antenna(orcable).SuggestedvaluesarelistedinTable15.

ThebalunandLCfiltercomponentvaluesandtheirplacementareimportanttokeeptheperformanceoptimized.ItishighlyrecommendedtofollowtheCC2500EMreferencedesign([4]).

Crystal

Thecrystaloscillatorusesanexternalcrystalwithtwoloadingcapacitors(C81andC101).SeeSection26onpage50fordetails.PowerSupplyDecoupling

Thepowersupplymustbeproperlydecoupledclosetothesupplypins.Notethatdecouplingcapacitorsarenotshownintheapplicationcircuit.Theplacementandthesizeofthedecouplingcapacitorsareveryimportanttoachievetheoptimumperformance.TheCC2500EMreferencedesign([4])shouldbefollowedclosely.

Component

C51C81/C101C121/C131C122/C132C123/C124L121/L131L122R171XTAL

Description

Decouplingcapacitorforon-chipvoltageregulatortodigitalpartCrystalloadingcapacitors,seeSection26onpage50fordetailsRFbalunDCblockingcapacitorsRFbalun/matchingcapacitorsRFLCfilter/matchingcapacitors

RFbalun/matchinginductors(inexpensivemulti-layertype)RFLCfilterinductor(inexpensivemulti-layertype)Resistorforinternalbiascurrentreference

26-27MHzcrystal,seeSection26onpage50fordetails

Table14:OverviewofExternalComponents(excludingsupplydecouplingcapacitors)

1.8V-3.6VpowersupplyR171SISI20GND19DGUARD18RBIAS17GND16SCLK1SCLK2SO(GDO1)3GDO24DVDD5DCOUPL6GDO07CSnAVDD15AVDD14Antenna(50Ohm)L131C131C121L121C122C132L122C123DigitalIntefaceSO(GDO1)GDO2(optional)CC2500DIEATTACHPAD:10XOSC_Q28XOSC_Q19AVDDRF_N13RF_P12AVDD11C124C51GDO0(optional)CSnXTALC81

C101

Alternative:FoldeddipolePCBantenna(noexternalcomponentsneeded)Figure3:TypicalApplicationandEvaluationCircuit(excludingsupplydecouplingcapacitors)

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CC2500Component

C51C81C101C121C122C123C124C131C132L121L122L131R171XTAL

Value

100nF±10%,0402X5R27pF±5%,0402NP027pF±5%,0402NP0100pF±5%,0402NP01.0pF±0.25pF,0402NP01.8pF±0.25pF,0402NP01.5pF±0.25pF,0402NP0100pF±5%,0402NP01.0pF±0.25pF,0402NP01.2nH±0.3nH,0402monolithic1.2nH±0.3nH,0402monolithic1.2nH±0.3nH,0402monolithic

56kΩ±1%,0402

26.0MHzsurfacemountcrystalManufacturerMurataGRM15seriesMurataGRM15seriesMurataGRM15seriesMurataGRM15seriesMurataGRM15seriesMurataGRM15seriesMurataGRM15seriesMurataGRM15seriesMurataGRM15seriesMurataLQG15HSseriesMurataLQG15HSseriesMurataLQG15HSseries

KoaRK73seriesNDK,AT-41CD2

Table15:BillOfMaterialsfortheApplicationCircuit

Measurementshavebeenperformedwithmulti-layerinductorsfromothermanufacturers(e.g.Würth)andthemeasurementresultswerethesameaswhenusingtheMuratapart.TheGerberfilesfortheCC2500EMreferencedesign([4])areavailablefromtheTIwebsite.

Figure4:CC2500EMReferenceDesign([4])

8ConfigurationOverview



Packetradiohardwaresupport

ForwardErrorCorrection(FEC)interleavingDataWhitening

Wake-On-Radio(WOR)

with

CC2500canbeconfiguredtoachieveoptimumperformanceformanydifferentapplications.ConfigurationisdoneusingtheSPIinterface.Thefollowingkeyparameterscanbeprogrammed:



Power-down/powerupmode

Crystaloscillatorpower-up/power-downReceive/transmitmodeRFchannelselectionDatarate

Modulationformat

RXchannelfilterbandwidthRFoutputpower

Databufferingwithseparate-bytereceiveandtransmitFIFOs

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DetailsofeachconfigurationregistercanbefoundinSection32,startingonpage57.Figure5showsasimplifiedstatediagramthatexplainsthemainCC2500states,togetherwithtypicalusageandcurrentconsumption.FordetailedinformationoncontrollingtheCC2500statemachine,andacompletestatediagram,seeSection19,startingonpage39.

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CC2500Lowestpowermode.Mostregistervaluesareretained.Typ.currentconsumption400nA,or900nAwhenwake-on-radio(WOR)isenabled.SleepSIDLESPWDorwake-on-radio(WOR)Defaultstatewhentheradioisnotreceivingortransmitting.Typ.currentconsumption:1.5mA.CSn=0IdleSXOFFSCALUsedforcalibratingfrequencysynthesizerupfront(enteringCSn=0receiveortransmitmodecanManualfreq.thenbedonequicker).synth.calibrationSRXorSTXorSFSTXONorwake-on-radio(WOR)Transitionalstate.Typ.currentconsumption:7.4mA.

CrystaloscillatoroffAllregistervaluesareretained.Typ.currentconsumption;0.16mA.

Frequencysynthesizerison,readytostarttransmitting.TransmissionstartsveryquicklyafterreceivingtheSTXcommandstrobe.Typ.currentconsumption:7.4mA.SFSTXONFrequencysynthesizerstartup,optionalcalibration,settlingFrequencysynthesizeristurnedon,canoptionallybecalibrated,andthensettlestothecorrectfrequency.Transitionalstate.Typ.currentconsumption:7.4mA.

FrequencysynthesizeronSTXSRXorwake-on-radio(WOR)STXTXOFF_MODE=01SFSTXONorRXOFF_MODE=01Typ.currentconsumption:11.1mAat-12dBmoutput,15.1mAat-6dBmoutput,21.2mAat0dBmoutput.

TransmitmodeSTXorRXOFF_MODE=10ReceivemodeSRXorTXOFF_MODE=11Typ.currentconsumption:

from13.3mA(stronginputsignal)to16.6mA(weakinputsignal).

TXOFF_MODE=00RXOFF_MODE=00InFIFO-basedmodes,transmissionisturnedoffandthisstateenterediftheTXFIFObecomesemptyinthemiddleofapacket.Typ.currentconsumption:1.5mA.Optionaltransitionalstate.Typ.currentconsumption:7.4mA.TXFIFOunderflowOptionalfreq.synth.calibrationRXFIFOoverflowInFIFO-basedmodes,receptionisturnedoffandthisstateenterediftheRXFIFOoverflows.Typ.currentconsumption:1.5mA.SFTXSFRXIdleFigure5:SimplifiedStateDiagramwithTypicalUsageandCurrentConsumptionat250kBaud

DataRateandMDMCFG2.DEM_DCFILT_OFF=1(currentoptimized)

9ConfigurationSoftware

Afterchipreset,alltheregistershavedefaultvaluesasshowninthetablesinSection32.Theoptimumregistersettingmightdifferfromthedefaultvalue.AfteraresetallregistersthatshallbedifferentfromthedefaultvaluethereforeneedstobeprogrammedthroughtheSPIinterface.

CC2500canbeconfiguredusingtheSmartRFStudiosoftware[5].TheSmartRFStudiosoftwareishighlyrecommendedforobtainingoptimumregistersettings,andforevaluatingperformanceandfunctionality.AscreenshotoftheSmartRFStudiouserinterfaceforCC2500isshowninFigure6.

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CC2500Figure6:SmartRFStudio[5]UserInterface

104-wireSerialConfigurationandDataInterface

CC2500isconfiguredviaasimple4-wireSPI-compatibleinterface(SI,SO,SCLKandCSn)whereCC2500istheslave.Thisinterfaceisalsousedtoreadandwritebuffereddata.AlltransfersontheSPIinterfacearedonemostsignificantbitfirst.

AlltransactionsontheSPIinterfacestartwithaheaderbytecontainingaR/Wbit,aburstaccessbit(B),anda6-bitaddress(A5–A0).TheCSnpinmustbekeptlowduringtransfersontheSPIbus.IfCSngoeshighduringthe

transferofaheaderbyteorduringread/writefrom/toaregister,thetransferwillbecancelled.ThetimingfortheaddressanddatatransferontheSPIinterfaceisshowninFigure7withreferencetoTable16.

WhenCSnispulledlow,theMCUmustwaituntilCC2500SOpingoeslowbeforestartingtotransfertheheaderbyte.Thisindicatesthatthecrystalisrunning.UnlessthechipwasintheSLEEPorXOFFstates,theSOpinwillalwaysgolowimmediatelyaftertakingCSnlow.

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CC2500Figure7:ConfigurationRegisterWriteandReadOperations

ParameterfSCLK

DescriptionSCLKfrequency

100nsdelayinsertedbetweenaddressbyteanddatabyte(singleaccess),orbetweenaddressanddata,andbetweeneachdatabyte(burstaccess).

Min-

Max10

UnitsMHz

SCLKfrequency,singleaccess

Nodelaybetweenaddressanddatabyte

96.5

150205050--SingleaccessBurstaccess

55762020

---55----

MHzMHzµsnsnsnsnsnsnsnsnsns

SCLKfrequency,burstaccess

Nodelaybetweenaddressanddatabyte,orbetweendatabytes

tsp,pdtsptchtcltrisetfalltsd

CSnlowtopositiveedgeonSCLK,inpower-downmodeCSnlowtopositiveedgeonSCLK,inactivemodeClockhighClocklowClockrisetimeClockfalltime

Setupdata(negativeSCLKedge)topositiveedgeonSCLK

(tsdappliesbetweenaddressanddatabytes,andbetweendatabytes)

thdtns

HolddataafterpositiveedgeonSCLKNegativeedgeonSCLKtoCSnhigh

Table16:SPIInterfaceTimingRequirements

Note:Theminimumtsp,pdfigureinTable16canbeusedincaseswheretheuserdoesnotreadtheCHIP_RDYnsignal.CSnlowtopositiveedgeonSCLKwhenthechipiswokenfrompower-downdependsonthestart-uptimeofthecrystalbeingused.The150usinTable16isthecrystaloscillatorstart-uptimemeasuredonCC2500EMreferencedesign([4])usingcrystalAT-41CD2fromNDK.10.1

ChipStatusByte

beforethefirstpositiveedgeofSCLK.TheCHIP_RDYnsignalindicatesthatthecrystalisrunning.

Bits6,5,and4comprisetheSTATEvalue.Thisvaluereflectsthestateofthechip.TheXOSCandpowertothedigitalcoreisonintheIDLEstate,butallothermodulesareinpowerdown.Thefrequencyandchannel

Page22of

Whentheheaderbyte,databyteor,commandstrobeissentontheSPIinterface,thechipstatusbyteissentbytheCC2500ontheSOpin.Thestatusbytecontainskeystatussignals,usefulfortheMCU.Thefirstbit,s7,istheCHIP_RDYnsignal;thissignalmustgolow

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CC2500configurationshouldonlybeupdatedwhenthechipisinthisstate.TheRXstatewillbeactivewhenthechipisinreceivemode.Likewise,TXisactivewhenthechipistransmitting.

Thelastfourbits(3:0)inthestatusbytecontainsFIFO_BYTES_AVAILABLE.Forreadoperations(theR/Wbitintheheaderbyteissetto1),theFIFO_BYTES_AVAILABLEfieldcontainsthenumberofbytesavailablefor

readingfromtheRXFIFO.Forwriteoperations(theR/Wbitintheheaderbyteissetto0),theFIFO_BYTES_AVAILABLEfieldcontainsthenumberofbytesthatcanbewrittentotheTXFIFO.WhenFIFO_BYTES_AVAILABLE=15,15ormorebytesareavailable/free.

Table17givesastatusbytesummary.

Bits76:4

NameCHIP_RDYnSTATE[2:0]

Description

Stayshighuntilpowerandcrystalhavestabilized.ShouldalwaysbelowwhenusingtheSPIinterface.

IndicatesthecurrentmainstatemachinemodeValue000

StateIDLE

Description

Idlestate

(AlsoreportedforsometransitionalstatesinsteadofSETTLINGorCALIBRATE)ReceivemodeTransmitmode

Frequencysynthesizerison,readytostarttransmitting

FrequencysynthesizercalibrationisrunningPLLissettling

RXFIFOhasoverflowed.Readoutanyusefuldata,thenflushtheFIFOwithSFRXTXFIFOhasunderflowed.AcknowledgewithSFTX

001010011100101110111

3:0

FIFO_BYTES_AVAILABLE[3:0]

RXTXFSTXONCALIBRATESETTLING

RXFIFO_OVERFLOWTXFIFO_UNDERFLOW

ThenumberofbytesavailableintheRXFIFOorfreebytesintheTXFIFO

Table17:StatusByteSummary

10.2

RegisterAccess

burstbit(B)intheheaderbyte.Theaddressbits(A5–A0)setthestartaddressinaninternaladdresscounter.Thiscounterisincrementedbyoneeachnewbyte(every8clockpulses).TheburstaccessiseitherareadorawriteaccessandmustbeterminatedbysettingCSnhigh.

Forregisteraddressesintherange0x30-0x3D,theburstbitisusedtoselectbetweenstatusregisters,burstbitisone,andcommandstrobes,burstbitiszero(seeSection10.4below).Becauseofthis,burstaccessisnotavailableforstatusregistersandtheymustbeaccessedoneatatime.Thestatusregisterscanonlyberead.10.3

SPIRead

TheconfigurationregistersoftheCC2500arelocatedonSPIaddressesfrom0x00to0x2E.Table35onpage58listsallconfigurationregisters.Itishighlyrecommendedtouse

SmartRFStudio[5]togenerateoptimumregistersettings.ThedetaileddescriptionofeachregisterisfoundinSection32.1,startingonpage61.Allconfigurationregisterscanbebothwrittentoandread.TheR/Wbitcontrolsiftheregistershouldbewrittentoorread.Whenwritingtoregisters,thestatusbyteissentontheSOpineachtimeaheaderbyteordatabyteistransmittedontheSIpin.Whenreadingfromregisters,thestatusbyteissentontheSOpineachtimeaheaderbyteistransmittedontheSIpin.

Registerswithconsecutiveaddressescanbeaccessedinanefficientwaybysettingthe

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WhenreadingregisterfieldsovertheSPIinterfacewhiletheregisterfieldsareupdated

Page23of

CC2500bytheradiohardware(e.g.MARCSTATEorTXBYTES),thereisasmall,butfinite,probabilitythatasinglereadfromtheregisterisbeingcorrupt.Asanexample,theprobabilityofanysinglereadfromTXBYTESbeingcorrupt,assumingthemaximumdatarateisused,isapproximately80ppm.RefertotheCC2500ErrataNotes[1]formoredetails.10.4

CommandStrobes

TheTXFIFOiswrite-only,whiletheRXFIFOisread-only.

TheburstbitisusedtodetermineiftheFIFOaccessisasinglebyteaccessoraburstaccess.Thesinglebyteaccessmethodexpectsaheaderbytewiththeburstbitsettozeroandonedatabyte.Afterthedatabyteanewheaderbyteisexpected;hence,CSncanremainlow.TheburstaccessmethodexpectsoneheaderbyteandthenconsecutivedatabytesuntilterminatingtheaccessbysettingCSnhigh.

ThefollowingheaderbytesaccesstheFIFOs:

0x3F:SinglebyteaccesstoTXFIFO0x7F:BurstaccesstoTXFIFO0xBF:SinglebyteaccesstoRXFIFO0xFF:BurstaccesstoRXFIFO

CommandstrobesmaybeviewedassinglebyteinstructionstoCC2500.Byaddressingacommandstroberegister,internalsequenceswillbestarted.Thesecommandsareusedtodisablethecrystaloscillator,enablereceivemode,enablewake-on-radioetc.The13commandstrobesarelistedinTable34onpage57.

Thecommandstroberegistersareaccessedbytransferringasingleheaderbyte(nodataisbeingtransferred).Thatis,onlytheR/Wbit,theburstaccessbit(setto0),andthesixaddressbits(intherange0x30through0x3D)arewritten.TheR/WbitcanbeeitheroneorzeroandwilldeterminehowtheFIFO_BYTES_AVAILABLEfieldinthestatusbyteshouldbeinterpreted.

Whenwritingcommandstrobes,thestatusbyteissentontheSOpin.

AcommandstrobemaybefollowedbyanyotherSPIaccesswithoutpullingCSnhigh.However,ifanSRESstrobeisbeingissued,onewillhavetowaitforSOtogolowagainbeforethenextheaderbytecanbeissuedasshowninFigure8.Thecommandstrobesareexecutedimmediately,withtheexceptionoftheSPWDandtheSXOFFstrobesthatareexecutedwhenCSngoeshigh.

WhenwritingtotheTXFIFO,thestatusbyte(seeSection10.1)isoutputforeachnewdatabyteonSO,asshowninFigure7.ThisstatusbytecanbeusedtodetectTXFIFOunderflowwhilewritingdatatotheTXFIFO.NotethatthestatusbytecontainsthenumberofbytesfreebeforewritingthebyteinprogresstotheTXFIFO.WhenthelastbytethatfitsintheTXFIFOistransmittedonSI,thestatusbytereceivedconcurrentlyonSOwillindicatethatonebyteisfreeintheTXFIFO.

TheTXFIFOmaybeflushedbyissuingaSFTXcommandstrobe.Similarly,aSFRXcommandstrobewillflushtheRXFIFO.ASFTXorSFRXcommandstrobecanonlybeissuedintheIDLE,TXFIFO_UNDERLOWorRXFIFO_OVERFLOWstates.BothFIFOsareflushedwhengoingtotheSLEEPstate.Figure9givesabriefoverviewofdifferentregisteraccesstypespossible.10.6

PATABLEAccess

Figure8:SRESCommandStrobe10.5

FIFOAccess

The-byteTXFIFOandthe-byteRXFIFOareaccessedthroughthe0x3Faddress.WhentheR/Wbitiszero,theTXFIFOisaccessed,andtheRXFIFOisaccessedwhentheR/Wbitisone.

The0x3EaddressisusedtoaccessthePATABLE,whichisusedforselectingPApowercontrolsettings.ThePATABLEisan8-bytetable,butnotallentriesintothistableareused.Theentriestouseareselectedbythe3-bitvalueFREND0.PA_POWER.

Whenusing2-FSK,GFSK,orMSKmodulationonlythefirstentryintothistableisused(index0).

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CC2500

WhenusingOOKmodulationthefirsttwoentriesintothistableareused(index0andindex1).

accessisawriteaccess(R/W=0)orareadaccess(R/W=1).

IfonebyteiswrittentothePATABLEandthisvalueistobereadoutthenCSnmustbesethighbeforethereadaccessinordertosettheindexcounterbacktozero.

NotethatthecontentofthePATABLEislostwhenenteringtheSLEEPstate,exceptforthefirstbyte(index0).

SeeSection24onpage46foroutputpowerprogrammingdetails.

SincethePATABLEisan8-bytetable,thetableiswrittenandreadfromthelowestsetting(0)tothehighest(7),onebyteatatime.Anindexcounterisusedtocontroltheaccesstothetable.Thiscounterisincrementedeachtimeabyteisreadorwrittentothetable,andsettothelowestindexwhenCSnishigh.Whenthehighestvalueisreachedthecounterrestartsat0.

TheaccesstothePATABLEiseithersinglebyteorburstaccessdependingontheburstbit.Whenusingburstaccesstheindexcounterwillcountup;whenreaching7thecounterwillrestartat0.TheR/Wbitcontrolswhetherthe

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CC2500TheGDO0pincanalsobeusedforanon-chipanalogtemperaturesensor.BymeasuringthevoltageontheGDO0pinwithanexternalADC,thetemperaturecanbecalculated.SpecificationsforthetemperaturesensorarefoundinSection4.7onpage14.

WithdefaultPTESTregistersetting(0x7F)thetemperaturesensoroutputisonlyavailablewhenthefrequencysynthesizerisenabled(e.g.theMANCAL,FSTXON,RXandTXstates).Itisnecessarytowrite0xBFtothePTESTregistertousetheanalogtemperaturesensorintheIDLEstate.BeforeleavingtheIDLEstate,thePTESTregistershouldberestoredtoitsdefaultvalue(0x7F).11.3

OptionalRadioControlFeature

Statechangesarecommandedasfollows:WhenCSnishightheSIandSCLKissettothedesiredstateaccordingtoTable18.WhenCSngoeslowthestateofSIandSCLKislatchedandacommandstrobeisgeneratedinternallyaccordingtothecontrolcoding.Itisonlypossibletochangestatewiththisfunctionality.ThatmeansthatforinstanceRXwillnotberestartedifSIandSCLKaresettoRXandCSntoggles.WhenCSnislowtheSIandSCLKhasnormalSPIfunctionality.Allpincontrolcommandstrobesareexecutedimmediately,excepttheSPWDstrobe,whichisdelayeduntilCSngoeshigh.

CSn

10

SCLK

X0011SPImode

X0101SPImode

Function

ChipunaffectedbySCLK/SIGeneratesSPWDstrobeGeneratesSTXstrobeGeneratesSIDLEstrobeGeneratesSRXstrobeSPImode(wakesupintoIDLEifinSLEEP/XOFF)

TheCC2500hasanoptionalwayofcontrollingtheradio,byreusingSI,SCLKandCSnfromtheSPIinterface.Thisfeatureallowsforasimplethree-pincontrolofthemajorstatesoftheradio:SLEEP,IDLE,RXandTX.

ThisoptionalfunctionalityisenabledwiththeMCSM0.PIN_CTRL_ENconfigurationbit.

Table18:OptionalPinControlCoding

12DataRateProgramming

Thedatarateusedwhentransmitting,orthedatarateexpectedinreceiveisprogrammedbytheMDMCFG3.DRATE_MandtheMDMCFG4.DRATE_Econfigurationregisters.Thedatarateisgivenbytheformulabelow.Astheformulashows,theprogrammeddataratedependsonthecrystalfrequency.

IfDRATE_Misroundedtothenearestintegerandbecomes256,incrementDRATE_EanduseDRATE_M=0.

Thedataratecanbesetfrom1.2kBaudto500kBaudwiththeminimumstepsizeof:

RDATA

256DRATE_M2DRATE_Ef

228

MinData

Rate[kBaud]

XOSC

TypicalDataRate[kBaud]1.2/2.44..619.638.476.8153.6250500

MaxDataRate[kBaud]3.176.3512.725.450.8101.6203.1406.3500

DataRateStepSize[kBaud]0.00620.01240.02480.04960.09920.19840.39670.79351.5869

0.83.17

Thefollowingapproachcanbeusedtofindsuitablevaluesforagivendatarate:

6.3512.725.4

RDATA220

DRATE_Elog2f

XOSC

RDATA228

DRATE_M256DRATE_E

fXOSC2

50.8101.6203.1406.3

Table19:DataRateStepSize

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CC250013ReceiverChannelFilterBandwidth

Inordertomeetdifferentchannelwidthrequirements,thereceiverchannelfilterisprogrammable.TheMDMCFG4.CHANBW_EandMDMCFG4.CHANBW_Mconfigurationregisterscontrolthereceiverchannelfilterbandwidth,whichscaleswiththecrystaloscillatorfrequency.Thefollowingformulagivestherelationbetweentheregistersettingsandthechannelfilterbandwidth:

kHz,whichis480kHz.Assuming2.44GHzfrequencyand±20ppmfrequencyuncertaintyforboththetransmittingdeviceandthereceivingdevice,thetotalfrequencyuncertaintyis±40ppmof2.44GHz,whichis±98kHz.Ifthewholetransmittedsignalbandwidthistobereceivedwithin480kHz,thetransmittedsignalbandwidthshouldbemaximum480kHz–2·98kHz,whichis284kHz.

TheCC2500supportsthefollowingchannelfilterbandwidths:

BWchannel

fXOSC

8(4CHANBW_M)·2CHANBW_E

MDMCFG4.MDMCFG4.CHANBW_E0081265014

01406325270232

10203162135116

11102816858

Forbestperformance,thechannelfilterbandwidthshouldbeselectedsothatthesignalbandwidthoccupiesatmost80%ofthechannelfilterbandwidth.Thechannelcentretoleranceduetocrystalaccuracyshouldalsobesubtractedfromthesignalbandwidth.Thefollowingexampleillustratesthis:

Withthechannelfilterbandwidthsetto600kHz,thesignalshouldstaywithin80%of600

CHANBW_M

00011011

Table20:ChannelFilterBandwidths[kHz]

(assuminga26MHzcrystal)

14Demodulator,SymbolSynchronizerandDataDecision

CC2500containsanadvancedandhighlyconfigurabledemodulator.Channelfilteringandfrequencyoffsetcompensationisperformeddigitally.TogeneratetheRSSIlevel(seeSection17.3formoreinformation)thesignallevelinthechannelisestimated.Datafilteringisalsoincludedforenhancedperformance.

14.1

FrequencyOffsetCompensation

IftheFOCCFG.FOC_BS_CS_GATEbitisset,theoffsetcompensatorwillfreezeuntilcarriersenseasserts.ThismaybeusefulwhentheradioisinRXforlongperiodswithnotraffic,sincethealgorithmmaydrifttotheboundarieswhentryingtotracknoise.

Thetrackingloophastwogainfactors,whichaffectsthesettlingtimeandnoisesensitivityofthealgorithm.FOCCFG.FOC_PRE_Ksetsthegainbeforethesyncwordisdetected,andFOCCFG.FOC_POST_Kselectsthegainafterthesyncwordhasbeenfound.

NotethatfrequencyoffsetcompensationisnotsupportedforOOKmodulation.14.2

BitSynchronization

Whenusing2-FSK,GFSK,orMSKmodulation,thedemodulatorwillcompensatefortheoffsetbetweenthetransmitterandreceiverfrequency,withincertainlimits,byestimatingthecentreofthereceiveddata.ThisvalueisavailableintheFREQESTstatusregister.WritingthevaluefromFREQESTintoFSCTRL0.FREQOFFthefrequencysynthesizerisautomaticallyadjustedaccordingtotheestimatedfrequencyoffset.ThetrackingrangeofthealgorithmisselectableasfractionsofthechannelbandwidthwiththeFOCCFG.FOC_LIMITconfigurationregister.

SWRS040C

Thebitsynchronizationalgorithmextractstheclockfromtheincomingsymbols.ThealgorithmrequiresthattheexpecteddatarateisprogrammedasdescribedinSection12onpage26.Re-synchronizationisperformedcontinuouslytoadjustforerrorintheincomingsymbolrate.

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CC250014.3

ByteSynchronization

Bytesynchronizationisachievedbyacontinuoussyncwordsearch.Thesyncwordisa16bitconfigurablefield(canberepeatedtogeta32bit)thatisautomaticallyinsertedatthestartofthepacketbythemodulatorintransmitmode.Thedemodulatorusesthisfieldtofindthebyteboundariesinthestreamofbits.Thesyncwordwillalsofunctionasasystemidentifier,sinceonlypacketswiththecorrectpredefinedsyncwordwillbereceivedifthesyncworddetectioninRXisenabledinregisterMDMCFG2(seeSection17.1).Thesyncworddetectorcorrelatesagainsttheuser-configured16or32bitsyncword.The

correlationthresholdcanbesetto15/16,16/16,or30/32bitsmatch.Thesyncwordcanbefurtherqualifiedusingthepreamblequalityindicatormechanismdescribedbelowand/oracarriersensecondition.ThesyncwordisconfiguredthroughtheSYNC1andSYNC0registers.

Inordertomakefalsedetectionsofsyncwordslesslikely,amechanismcalledpreamblequalityindication(PQI)canbeusedtoqualifythesyncword.Athresholdvalueforthepreamblequalitymustbeexceededinorderforadetectedsyncwordtobeaccepted.SeeSection17.2onpage34formoredetails.

15PacketHandlingHardwareSupport

TheCC2500hasbuilt-inhardwaresupportforpacketorientedradioprotocols.

Intransmitmode,thepackethandlercanbeconfiguredtoaddthefollowingelementstothepacketstoredintheTXFIFO:

Aprogrammablenumberofpreamblebytes

Atwobytesynchronization(sync)word.Canbeduplicatedtogivea4-bytesyncword(recommended).Itisnotpossibletoonlyinsertpreambleoronlyinsertasyncword.

ACRCchecksumcomputedoverthedatafield



Onebyteaddresscheck

Packetlengthcheck(lengthbytecheckedagainstaprogrammablemaximumlength)De-whitening

De-interleavinganddecoding

Optionally,twostatusbytes(seeTable21andTable22)withRSSIvalue,LinkQualityIndication,andCRCstatuscanbeappendedintheRXFIFO.



Bit7:0

FieldNameRSSI

DescriptionRSSIvalue

Therecommendedsettingis4-bytepreambleand4-bytesyncword,exceptfor500kBauddataratewheretherecommendedpreamblelengthis8bytes.

Bit

Table21:ReceivedPacketStatusByte1(firstbyteappendedafterthedata)

FieldNameCRC_OK

Description

1:CRCforreceiveddataOK(orCRCdisabled)

0:CRCerrorinreceiveddata

Inaddition,thefollowingcanbeimplementedonthedatafieldandtheoptional2-byteCRCchecksum:

WhiteningofthedatawithaPN9sequence.

Forwarderrorcorrectionbytheuseofinterleavingandcodingofthedata(convolutionalcoding).

6:0LQI

TheLinkQualityIndicator

estimateshoweasilyareceivedsignalcanbedemodulated

Table22:ReceivedPacketStatusByte2(secondbyteappendedafterthedata)NotethatregisterfieldsthatcontrolthepackethandlingfeaturesshouldonlybealteredwhenCC2500isintheIDLEstate.

Inreceivemode,thepackethandlingsupportwillde-constructthedatapacketbyimplementingthefollowing(ifenabled):

PreambledetectionSyncworddetection

CRCcomputationandCRCcheck

SWRS040C

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CC250015.1

DataWhitening

Fromaradioperspective,theidealovertheairdataarerandomandDCfree.Thisresultsinthesmoothestpowerdistributionovertheoccupiedbandwidth.Thisalsogivestheregulationloopsinthereceiveruniformoperationconditions(nodatadependencies).Realworlddataoftencontainlongsequencesofzerosandones.Performancecanthenbeimprovedbywhiteningthedatabeforetransmitting,andde-whiteningthedatainthereceiver.WithCC2500,thiscanbedone

automaticallybysettingPKTCTRL0.WHITE_DATA=1.Alldata,exceptthepreambleandthesyncword,arethenXOR-edwitha9-bitpseudo-random(PN9)sequencebeforebeingtransmittedasshowninFigure10.Atthereceiverend,thedataareXOR-edwiththesamepseudo-randomsequence.Thisway,thewhiteningisreversed,andtheoriginaldataappearinthereceiver.ThePN9sequenceisresettoall1’s.

DatawhiteningcanonlybeusedwhenPKTCTRL0.CC2400_EN=0(default).

SWRS040CPage29of

CC2500Thepreamblepatternisanalternatingsequenceofonesandzeros(101010101…).Theminimumlengthofthepreambleisprogrammable.WhenenablingTX,themodulatorwillstarttransmittingthepreamble.Whentheprogrammednumberofpreamblebyteshasbeentransmitted,themodulatorwillsendthesyncwordandthendatafromtheTXFIFOifdataisavailable.IftheTXFIFOisempty,themodulatorwillcontinuetosendpreamblebytesuntilthefirstbyteiswrittentotheTXFIFO.Themodulatorwillthensendthesyncwordandthenthedatabytes.ThenumberofpreamblebytesisprogrammedwiththeMDMCFG1.NUM_PREAMBLEvalue.

Thesynchronizationwordisatwo-bytevaluesetintheSYNC1andSYNC0registers.Thesyncwordprovidesbytesynchronizationoftheincomingpacket.Aone-bytesyncwordcanbeemulatedbysettingtheSYNC1valuetothepreamblepattern.Itisalsopossibletoemulatea32bitsyncwordbyusingMDMCFG2.SYNC_MODE=3or7.Thesyncwordwillthenberepeatedtwice.

totheCC2500details.

ErrataNotes[1]formore

Notethattheminimumpacketlengthsupported(excludingtheoptionallengthbyteandCRC)isonebyteofpayloaddata.15.2.1ArbitraryLengthFieldConfigurationThepacketlengthregister,PKTLEN,canbereprogrammedduringreceiveandtransmit.Incombinationwithfixedpacketlengthmode(PKTCTRL0.LENGTH_CONFIG=0)thisopensthepossibilitytohaveadifferentlengthfieldconfigurationthansupportedforvariablelengthpackets(invariablepacketlengthmodethelengthbyteisthefirstbyteafterthesyncword).Atthestartofreception,thepacketlengthissettoalargevalue.TheMCUreadsoutenoughbytestointerpretthelengthfieldinthepacket.ThenthePKTLENvalueissetaccordingtothisvalue.TheendofpacketwilloccurwhenthebytecounterinthepackethandlerisequaltothePKTLENregister.Thus,theMCUmustbeabletoprogramthecorrectlength,beforetheinternalcounterreachesthepacketlength.

15.2.2PacketLength>256bytes

Alsothepacketautomationcontrolregister,PKTCTRL0,canbereprogrammedduringTXandRX.Thisopensthepossibilitytotransmitandreceivepacketsthatarelongerthan256bytesandstillbeabletousethepackethandlinghardwaresupport.Atthestartofthepacket,theinfinitepacketlengthmode(PKTCTRL0.LENGTH_CONFIG=2)mustbeactive.OntheTXside,thePKTLENregisterissettomod(length,256).OntheRXsidetheMCUreadsoutenoughbytestointerpretthelengthfieldinthepacketandsetsthePKTLENregistertomod(length,256).Whenlessthan256bytesremainsofthepackettheMCUdisablesinfinitepacketlengthmodeandactivatesfixedpacketlengthmode.WhentheinternalbytecounterreachesthePKTLENvalue,thetransmissionorreceptionends(theradioentersthestatedeterminedbyTXOFF_MODEorRXOFF_MODE).AutomaticCRCappending/checkingcanalsobeused(bysettingPKTCTRL0.CRC_EN=1).

Whenforexamplea600-bytepacketistobetransmitted,theMCUshoulddothefollowing(seealsoFigure12):

SetPKTCTRL0.LENGTH_CONFIG=2.

CC2500supportsbothfixedpacketlengthprotocolsandvariablepacketlengthprotocols.Variableorfixedpacketlengthmodecanbeusedforpacketsupto255bytes.Forlongerpackets,infinitepacketlengthmodemustbeused.

FixedpacketlengthmodeisselectedbysettingPKTCTRL0.LENGTH_CONFIG=0.ThedesiredpacketlengthissetbythePKTLENregister.

Invariablepacketlengthmode,PKTCTRL0.LENGTH_CONFIG=1,thepacketlengthisconfiguredbythefirstbyteafterthesyncword.Thepacketlengthisdefinedasthepayloaddata,excludingthelengthbyteandtheoptionalCRC.ThePKTLENregisterisusedtosetthemaximumpacketlengthallowedinRX.AnypacketreceivedwithalengthbytewithavaluegreaterthanPKTLENwillbediscarded.

WithPKTCTRL0.LENGTH_CONFIG=2,thepacketlengthissettoinfiniteandtransmissionandreceptionwillcontinueuntilturnedoffmanually.Asdescribedinthenextsection,thiscanbeusedtosupportpacketformatswithdifferentlengthconfigurationthannativelysupportedbyCC2500.OneshouldmakesurethatTXmodeisnotturnedoffduringthetransmissionofthefirsthalfofanybyte.Refer

SWRS040C

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CC2500

Pre-programthePKTLENmod(600,256)=88.



SetPKTCTRL0.LENGTH_CONFIG=0.Thetransmissionendswhenthepacketcounterreaches88.Atotalof600bytesaretransmitted.

Transmitatleast345bytes,forexamplebyfillingthe-byteTXFIFOsixtimes(384bytestransmitted).

Internalbytecounterinpackethandlercountsfrom0to255andthenstartsat0again

0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,.......................

InfinitepacketlengthenabledFixedpacketlengthenabledwhenlessthan256bytesremainsofpacket

600bytestransmittedandreceived

Lengthfieldtransmittedandreceived.RxandTxPKTLENvaluesettomod(600,256)=88

Figure12:PacketLength>256

15.3

PacketFilteringinReceiveMode

receivemoderestarted(regardlessoftheMCSM1.RXOFF_MODEsetting).15.3.3CRCFiltering

ThefilteringofapacketwhenCRCcheckfailsisenabledbysettingPKTCTRL1.CRC_AUTOFLUSH=1.TheCRCautoflushfunctionwillflushtheentireRXFIFOiftheCRCcheckfails.AfterautoflushingtheRXFIFO,thenextstatedependsontheMCSM1.RXOFF_MODEsetting.PKTCTRL0.CC2400_ENmustbe0(default)fortheCRCautoflushfunctiontoworkcorrectly.

Whenusingtheautoflushfunction,themaximumpacketlengthis63bytesinvariablepacketlengthmodeandbytesinfixedpacketlengthmode.NotethatthemaximumallowedpacketlengthisreducedbytwobyteswhenPKTCTRL1.APPEND_STATUSisenabled,tomakeroomintheRXFIFOforthetwostatusbytesappendedattheendofthepacket.SincetheentireRXFIFOisflushedwhentheCRCcheckfails,thepreviouslyreceivedpacketmustbereadoutoftheFIFObeforereceivingthecurrentpacket.TheMCUmustnotreadfromthecurrentpacketuntiltheCRChasbeencheckedasOK.15.4

CRCCheck

CC2500supportsthreedifferenttypesofpacket-filtering:addressfiltering,maximumlengthfilteringandCRCfiltering.

15.3.1AddressFiltering

SettingPKTCTRL1.ADR_CHKtoanyothervaluethanzeroenablesthepacketaddressfilter.ThepackethandlerenginewillcomparethedestinationaddressbyteinthepacketwiththeprogrammednodeaddressintheADDRregisterandthe0x00broadcastaddresswhenPKTCTRL1.ADR_CHK=10borboth0x00and0xFFbroadcastaddresseswhenPKTCTRL1.ADR_CHK=11b.Ifthereceivedaddressmatchesavalidaddress,thepacketisreceivedandwrittenintotheRXFIFO.Iftheaddressmatchfails,thepacketisdiscardedandreceivemoderestarted(regardlessoftheMCSM1.RXOFF_MODEsetting).

Ifthereceivedaddressmatchesavalidaddresswhenusinginfinitepacketlengthmodeandaddressfilteringisenabled,0xFFwillbewrittenintotheRXFIFOfollowedbytheaddressbyteandthenthepayloaddata.15.3.2MaximumLengthFiltering

Invariablepacketlengthmode,PKTCTRL0.LENGTH_CONFIG=1,thePKTLEN.PACKET_LENGTHregistervalueisusedtosetthemaximumallowedpacketlength.Ifthereceivedlengthbytehasalargervaluethanthis,thepacketisdiscardedand

SWRS040C

TherearetwodifferentCRCimplementations.PKTCTRL0.CC2400_ENselectsbetweenthe2options.TheCRCcheckisdifferentforthe2

Page31of

CC2500options.ReferalsototheCC2500ErrataNotes[1].

15.4.1PKTCTRL0.CC2400_EN=0

IfPKTCTRL0.CC2400_EN=0itispossibletoreadbacktheCRCstatusin2differentways:1)SetPKTCTRL1.APPEND_STATUS=1andreadtheCRC_OKflagintheMSBofthesecondbyteappendedtotheRXFIFOafterthepacketdata.Thisrequiresdoublebufferingofthepacket,i.e.theentirepacketcontentoftheRXFIFOmustbecompletelyreadoutbeforeitispossibletocheckwhethertheCRCindicationisOKornot.

2)ToavoidreadingtheentireRXFIFO,anothersolutionistousethePKTCTRL1.CRC_AUTOFLUSHfeature.Ifthisfeatureisenabled,theentireRXFIFOwillbeflushediftheCRCcheckfails.IfGDOx_CFG=0x06theGDOxpinwillbeassertedwhenasyncwordisfound.TheGDOxpinwillbede-assertedattheendofthepacket.WhenthelatteroccurstheMCUshouldreadthenumberofbytesintheRXFIFOfromtheRXBYTES.NUM_RXBYTESstatusregister.IfRXBYTES.NUM_RXBYTES=0theCRCcheckfailedandtheFIFOisflushed.IfRXBYTES.NUM_RXBYTES>0theCRCcheckwasOKanddatacanbereadoutoftheFIFO.15.4.2PKTCTRL0.CC2400_EN=1

IfPKTCTRL0.CC2400_EN=1theCRCcanbecheckedasoutlinedin1)inSection15.4.1aswellasbyreadingtheCRC_OKflagavailableinthePKTSTATUS[7]register,intheLQI[7]statusregisterorfromoneoftheGDOpinsifGDOx_CFGis0x07or0x15.

ThePKTCTRL1.CRC_AUTOFLUSHordatawhiteningcannotbeusedwhenPKTCTRL0.CC2400_EN=1.15.5

PacketHandlinginTransmitMode

Themodulatorwillfirstsendtheprogrammednumberofpreamblebytes.IfdataisavailableintheTXFIFO,themodulatorwillsendthetwo-byte(optionally4-byte)syncwordandthenthepayloadintheTXFIFO.IfCRCisenabled,thechecksumiscalculatedoverallthedatapulledfromtheTXFIFOandtheresultissentastwoextrabytesfollowingthepayloaddata.IftheTXFIFOrunsemptybeforethecompletepackethasbeentransmitted,theradiowillenterTXFIFO_UNDERFLOWstate.TheonlywaytoexitthisstateisbyissuinganSFTXstrobe.WritingtotheTXFIFOafterithasunderflowedwillnotrestartTXmode.

Ifwhiteningisenabled,everythingfollowingthesyncwordswillbewhitened.ThisisdonebeforetheoptionalFEC/Interleaverstage.WhiteningisenabledbysettingPKTCTRL0.WHITE_DATA=1.

IfFEC/Interleavingisenabled,everythingfollowingthesyncwordswillbescrambledbytheinterleaverandFECencodedbeforebeingmodulated.FECisenabledbysettingMDMCFG1.FEC_EN=1.15.6

PacketHandlinginReceiveMode

Inreceivemode,thedemodulatorandpackethandlerwillsearchforavalidpreambleandthesyncword.Whenfound,thedemodulatorhasobtainedbothbitandbytesynchronismandwillreceivethefirstpayloadbyte.

IfFEC/Interleavingisenabled,theFECdecoderwillstarttodecodethefirstpayloadbyte.Theinterleaverwillde-scramblethebitsbeforeanyotherprocessingisdonetothedata.

Ifwhiteningisenabled,thedatawillbede-whitenedatthisstage.

Whenvariablepacketlengthmodeisenabled,thefirstbyteisthelengthbyte.Thepackethandlerstoresthisvalueasthepacketlengthandreceivesthenumberofbytesindicatedbythelengthbyte.Iffixedpacketlengthmodeisused,thepackethandlerwillaccepttheprogrammednumberofbytes.

Next,thepackethandleroptionallycheckstheaddressandonlycontinuesthereceptioniftheaddressmatches.IfautomaticCRCcheckisenabled,thepackethandlercomputesCRCandmatchesitwiththeappendedCRCchecksum.

Attheendofthepayload,thepackethandlerwilloptionallywritetwoextrapacketstatus

Page32of

ThepayloadthatistobetransmittedmustbewrittenintotheTXFIFO.Thefirstbytewrittenmustbethelengthbytewhenvariablepacketlengthisenabled.Thelengthbytehasavalueequaltothepayloadofthepacket(includingtheoptionaladdressbyte).Ifaddressrecognitionisenabledonthereceiver,thesecondbytewrittentotheTXFIFOmustbetheaddressbyte.Iffixedpacketlengthisenabled,thenthefirstbytewrittentotheTXFIFOshouldbetheaddress(ifthereceiverusesaddressrecognition).

SWRS040C

CC2500bytesthatcontainCRCstatus,linkqualityindicationandRSSIvalue.15.7

PacketHandlinginFirmware

informationonhowmanybytesareintheRXFIFOandTXFIFOrespectively.SeeTable33.b)SPIpolling

Whenimplementingapacketorientedradioprotocolinfirmware,theMCUneedstoknowwhenapackethasbeenreceived/transmitted.Additionally,forpacketslongerthanbytestheRXFIFOneedstobereadwhileinRXandtheTXFIFOneedstoberefilledwhileinTX.ThismeansthattheMCUneedstoknowthenumberofbytesthatcanbereadfromorwrittentotheRXFIFOandTXFIFOrespectively.Therearetwopossiblesolutionstogetthenecessarystatusinformation:a)Interruptdrivensolution

InbothRXandTXonecanuseoneoftheGDOpinstogiveaninterruptwhenasyncwordhasbeenreceived/transmittedand/orwhenacompletepackethasbeenreceived/transmitted(IOCFGx=0x06).Inaddition,therearetwoconfigurationsfortheIOCFGxregisterthatareassociatedwiththeRXFIFO(IOCFGx=0x00andIOCFGx=0x01)andtwothatareassociatedwiththeTXFIFO(IOCFGx=0x02andIOCFG=0x03)thatcanbeusedasinterruptsourcestoprovide

ThePKTSTATUSregistercanbepolledatagivenratetogetinformationaboutthecurrentGDO2andGDO0valuesrespectively.TheRXBYTESandTXBYTESregisterscanbepolledatagivenratetogetinformationaboutthenumberofbytesintheRXFIFOandTXFIFOrespectively.Alternatively,thenumberofbytesintheRXFIFOandTXFIFOcanbereadfromthechipstatusbytereturnedontheMISOlineeachtimeaheaderbyte,databyte,orcommandstrobeissentontheSPIbus.ItisrecommendedtoemployaninterruptdrivensolutionashighrateSPIpollingwillreducetheRXsensitivity.Furthermore,asexplainedinSection10.3andtheCC2500ErrataNotes[1],whenusingSPIpollingthereisasmall,butfinite,probabilitythatasinglereadfromregistersPKTSTATUS,RXBYTESandTXBYTESisbeingcorrupt.Thesameisthecasewhenreadingthechipstatusbyte.RefertotheTIwebsiteforSWexamples([6]and[7]).

16ModulationFormats

CC2500supportsamplitude,frequencyandphaseshiftmodulationformats.ThedesiredmodulationformatissetintheMDMCFG2.MOD_FORMATregister.

Optionally,thedatastreamcanbeManchestercodedbythemodulatoranddecodedbythedemodulator.ThisoptionisenabledbysettingMDMCFG2.MANCHESTER_EN=1.ManchesterencodingisnotsupportedatthesametimeasusingtheFEC/Interleaveroption.16.1

FrequencyShiftKeying

16.2

MinimumShiftKeying

fdev

fxosc

(8DEVIATION_M)2DEVIATION_E172

ThesymbolencodingisshowninTable23.

Format2-FSK/GFSK

Symbol‘0’‘1’

Coding–Deviation+Deviation

Table23:SymbolEncodingfor2-FSK/GFSK

Modulation

2-FSKcanoptionallybeshapedbyaGaussianfilterwithBT=1,producingaGFSKmodulatedsignal.

ThefrequencydeviationisprogrammedwiththeDEVIATION_MandDEVIATION_EvaluesintheDEVIATNregister.Thevaluehasanexponent/mantissaform,andtheresultantdeviationisgivenby:

WhenusingMSK,thecompletetransmission(preamble,syncwordandpayload)willbeMSKmodulated.

Phaseshiftsareperformedwithaconstanttransitiontime.

IdenticaltooffsetQPSKwithhalf-sineshaping(datacodingmaydiffer)

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SWRS040C

CC2500ThefractionofasymbolperiodusedtochangethephasecanbemodifiedwiththeDEVIATN.DEVIATION_Msetting.Thisisequivalenttochangingtheshapingofthesymbol.

TheMSKmodulationformatimplementedinCC2500invertsthesyncwordanddatacomparedtoe.g.signalgenerators.

16.3

AmplitudeModulation

ThesupportedamplitudemodulationOn-OffKeying(OOK)simplyturnsonoroffthePAtomodulate1and0respectively.

17ReceivedSignalQualifiersandLinkQualityInformation

CC2500hasseveralqualifiersthatcanbeusedtoincreasethelikelihoodthatavalidsyncwordisdetected.

17.1

SyncWordQualifier

Thepreamblequalityestimatorincreasesaninternalcounterbyoneeachtimeabitisreceivedthatisdifferentfromthepreviousbit,anddecreasesthecounterby8eachtimeabitisreceivedthatisthesameasthelastbit.ThethresholdisconfiguredwiththeregisterfieldPKTCTRL1.PQT.Athresholdof4∙PQTforthiscounterisusedtogatesyncworddetection.Bysettingthevaluetozero,thepreamblequalityqualifierofthesyncwordisdisabled.

A“PreambleQualityReached”signalcanbeobservedononeoftheGDOpinsbysettingIOCFGx.GDOx_CFG=8.ItisalsopossibletodetermineifpreamblequalityisreachedbycheckingthePQT_REACHEDbitinthePKTSTATUSregister.Thissignal/bitassertswhenthereceivedsignalexceedsthePQT.17.3

RSSI

IfsyncworddetectioninRXisenabledinregisterMDMCFG2theCC2500willnotstartfillingtheRXFIFOandperformthepacketfilteringdescribedinSection15.3beforeavalidsyncwordhasbeendetected.ThesyncwordqualifiermodeissetbyMDMCFG2.SYNC_MODEandissummarizedinTable24.CarriersenseinTable24isdescribedinSection17.4.

MDMCFG2.SYNC_MODE

000001010011100101110111

SyncWordQualifierModeNopreamble/sync

15/16syncwordbitsdetected16/16syncwordbitsdetected30/32syncwordbitsdetectedNopreamble/sync,carriersenseabovethreshold

15/16+carriersenseabovethreshold16/16+carriersenseabovethreshold30/32+carriersenseabovethreshold

TheRSSIvalueisanestimateofthesignallevelinthechosenchannel.ThisvalueisbasedonthecurrentgainsettingintheRXchainandthemeasuredsignallevelinthechannel.

InRXmode,theRSSIvaluecanbereadcontinuouslyfromtheRSSIstatusregisteruntilthedemodulatordetectsasyncword(whensyncworddetectionisenabled).AtthatpointtheRSSIreadoutvalueisfrozenuntilthenexttimethechipenterstheRXstate.TheRSSIvalueisindBmwith½dBresolution.TheRSSIupdaterate,fRSSI,dependsonthereceiverfilterbandwidth(BWchanneldefinedinSection13)andAGCCTRL0.FILTER_LENGTH.

Table24:SyncWordQualifierMode17.2

PreambleQualityThreshold(PQT)

ThePreambleQualityThreshold(PQT)sync-wordqualifieraddstherequirementthatthereceivedsyncwordmustbeprecededwithapreamblewithaqualityaboveaprogrammedthreshold.

AnotheruseofthepreamblequalitythresholdisasaqualifierfortheoptionalRXterminationtimer.SeeSection19.7onpage43fordetails.

SWRS040C

fRSSI

2BWchannel82FILTER_LENGTH

IfPKTCTRL1.APPEND_STATUSisenabledtheRSSIvalueatsyncworddetectionis

Page34of

CC2500automaticallyaddedtothefirstbyteappendedafterthedatapayload.

TheRSSIvaluereadfromtheRSSIstatusregisterisa2’scomplementnumber.ThefollowingprocedurecanbeusedtoconverttheRSSIreadingtoanabsolutepowerlevel(RSSI_dBm).

1)ReadtheRSSIstatusregister

2)Convertthereadingfromahexadecimal

numbertoadecimalnumber(RSSI_dec)3)IfRSSI_dec≥128thenRSSI_dBm=

(RSSI_dec-256)/2–RSSI_offset4)ElseifRSSI_dec<128thenRSSI_dBm=

(RSSI_dec)/2–RSSI_offset

Table25providestypicalvaluesfortheRSSI_offset.

Figure13showstypicalplotsofRSSIreadingsasafunctionofinputpowerlevelfordifferentdatarates.

DataRate[kBaud]

2.410250500

RSSI_offset[dB]

71697272

Table25:TypicalRSSI_offsetValues

0,0-10,0-20,0-30,0RSSIreadout[dBm]-40,0-50,0-60,0-70,0-80,0-90,0-100,0-110,0-120,0-120-110-100-90-80-70-60-50-40-30-20-100Inputpower[dBm]2.4kBaud10kBaud250kBaud250kBaud,reducedcurrent500kBaudFigure13:TypicalRSSIValuevs.InputPowerLevelforSomeTypicalDataRates

17.4

CarrierSense(CS)

de-assertedwhenRSSIhasdecreasedwiththesamenumberofdB.Thissettingisnotdependentontheabsolutesignallevelandisthususefultodetectsignalsinenvironmentswithatimevaryingnoisefloor.

CarrierSensecanbeusedasasyncwordqualifierthatrequiresthesignalleveltobehigherthanthethresholdforasyncwordsearchtobeperformed.ThesignalcanalsobeobservedononeoftheGDOpinsbysetting

Page35of

TheCarrierSense(CS)flagisusedasasyncwordqualifierandforCCA.TheCSflagcanbesetbasedontwoconditions,whichcanbeindividuallyadjusted:

CSisassertedwhentheRSSIisaboveaprogrammableabsolutethreshold,andde-assertedwhenRSSIisbelowthesamethreshold(withhysteresis).

CSisassertedwhentheRSSIhasincreasedwithaprogrammablenumberofdBfromoneRSSIsampletothenext,and

SWRS040C



CC2500IOCFGx.GDOx_CFG=14andinthestatusregisterbitPKTSTATUS.CS.

OtherusesofCarrierSenseincludetheTX-if-CCAfunction(seeSection17.5onpage37)andtheoptionalfastRXtermination(seeSection19.7onpage43).

CScanbeusedtoavoidinterferencefrome.g.WLAN.

17.4.1CSAbsoluteThreshold

TheabsolutethresholdrelatedtotheRSSIvaluedependsonthefollowingregisterfields:

AGCCTRL2.MAX_LNA_GAINAGCCTRL2.MAX_DVGA_GAIN

AGCCTRL1.CARRIER_SENSE_ABS_THRAGCCTRL2.MAGN_TARGET

000

MAX_LNA_GAIN[2:0]MAX_DVGA_GAIN[1:0]00

000

MAX_LNA_GAIN[2:0]01-93-90.5-87-86-84-82.5-78.5-76

10-87-85-82-80-78-76-73-70

11-81.5-78.5-76-74-72.5-70-67-

-99-97-93.5-91.5-90.5-88-84.5-82.5

001010011100101110111

Table26:TypicalRSSIValueindBmatCSThresholdwithDefaultMAGN_TARGETat2.4

kBaud

MAX_DVGA_GAIN[1:0]00-96-94.5-92.5-91-87.5-85-83-78

01-90--87-85-82-79.5-76.5-72

10-84-83-81-78.5-76-73.5-70.5-66

11-78.5-77.5-75-73-70-67.5-65-60

ForagivenAGCCTRL2.MAX_LNA_GAINandAGCCTRL2.MAX_DVGA_GAINsettingtheabsolutethresholdcanbeadjusted±7dBinstepsof1dBusingCARRIER_SENSE_ABS_THR.

TheMAGN_TARGETsettingisacompromisebetweenblockertolerance/selectivityandsensitivity.Thevaluesetsthedesiredsignallevelinthechannelintothedemodulator.Increasingthisvaluereducestheheadroomforblockers,andthereforeclose-inselectivity.

ItisstronglyrecommendedtouseSmartRFStudio[5]togeneratethecorrectMAGN_TARGETsetting.

Table26andTable27showthetypicalRSSIreadoutvaluesattheCSthresholdat2.4kBaudand250kBauddataraterespectively.ThedefaultCARRIER_SENSE_ABS_THR=0(0dB)andMAGN_TARGET=3(33dB)havebeenused.

ForotherdataratestheusermustgeneratesimilartablestofindtheCSabsolutethreshold.

001010011100101110111

Table27:TypicalRSSIValueindBmatCSThresholdwithDefaultMAGN_TARGETat250

kBaudIfthethresholdissethigh,i.e.onlystrongsignalsarewanted,thethresholdshouldbeadjustedupwardsbyfirstreducingtheMAX_LNA_GAINvalueandthentheMAX_DVGA_GAINvalue.Thiswillreducepowerconsumptioninthereceiverfrontend,sincethehighestgainsettingsareavoided.17.4.2CSRelativeThreshold

Therelativethresholddetectssuddenchangesinthemeasuredsignallevel.Thissettingisnotdependentontheabsolutesignallevelandisthususefultodetectsignalsinenvironmentswithatimevaryingnoisefloor.TheregisterfieldAGCCTRL1.CARRIER_SENSE_REL_THRisusedtoenable/disablerelativeCS,andtoselectthresholdof6dB,10dBor14dBRSSIchange

SWRS040CPage36of

CC250017.5

ClearChannelAssessment(CCA)



UnlesscurrentlyreceivingapacketBoththeabove(RSSIbelowthresholdandnotcurrentlyreceivingapacket)

LinkQualityIndicator(LQI)

TheClearChannelAssessmentCCA)isusedtoindicateifthecurrentchannelisfreeorbusy.ThecurrentCCAstateisviewableonanyoftheGDOpinsbysettingIOCFGx.GDOx_CFG=0x09.

MCSM1.CCA_MODEselectsthemodetousewhendeterminingCCA.

WhentheSTXorSFSTXONcommandstrobeisgivenwhileCC2500isintheRXstate,theTXorFSTXONstateisonlyenterediftheclearchannelrequirementsarefulfilled.ThechipwillotherwiseremaininRX(ifthechannelbecomesavailable,theradiowillnotenterTXorFSTXONstatebeforeanewstrobecommandissentontheSPIinterface).ThisfeatureiscalledTX-if-CCA.FourCCArequirementscanbeprogrammed:FourCCArequirementscanbeprogrammed:

Always(CCAdisabled,alwaysgoestoTX)IfRSSIisbelowthreshold

17.6

TheLinkQualityIndicatorisametricofthecurrentqualityofthereceivedsignal.IfPKTCTRL1.APPEND_STATUSisenabled,thevalueisautomaticallyaddedtothelastbyteappendedafterthepayload.ThevaluecanalsobereadfromtheLQIstatusregister.TheLQIgivesanestimateofhoweasilyareceivedsignalcanbedemodulatedbyaccumulatingthemagnitudeoftheerrorbetweenidealconstellationsandthereceivedsignaloverthesymbolsimmediatelyfollowingthesyncword.LQIisbestusedasarelativemeasurementofthelinkquality(ahighvalueindicatesabetterlinkthanwhatalowvaluedoes),sincethevalueisdependentonthemodulationformat.

18ForwardErrorCorrectionwithInterleaving

18.1

ForwardErrorCorrection(FEC)

CC2500hasbuiltinsupportforForwardErrorCorrection(FEC).Toenablethisoption,setMDMCFG1.FEC_ENto1.FECisonlysupportedinfixedpacketlengthmode(PKTCTRL0.LENGTH_CONFIG=0).FECisemployedonthedatafieldandCRCwordinordertoreducethegrossbiterrorratewhenoperatingnearthesensitivitylimit.Redundancyisaddedtothetransmitteddatainsuchawaythatthereceivercanrestoretheoriginaldatainthepresenceofsomebiterrors.

TheuseofFECallowscorrectreceptionatalowerSNR,thusextendingcommunicationrange.Alternatively,foragivenSNR,usingFECdecreasesthebiterrorrate(BER).Asthepacketerrorrate(PER)isrelatedtoBERby:

produceoccasionalerrorseveninotherwisegoodreceptionconditions.FECwillmasksucherrorsand,combinedwithinterleavingofthecodeddata,evencorrectrelativelylongperiodsoffaultyreception(bursterrors).TheFECschemeadoptedforCC2500isconvolutionalcoding,inwhichnbitsaregeneratedbasedonkinputbitsandthemmostrecentinputbits,formingacodestreamabletowithstandacertainnumberofbiterrorsbetweeneachcodingstate(them-bitwindow).Theconvolutionalcoderisarate1/2codewithaconstraintlengthofm=4.Thecodercodesoneinputbitandproducestwooutputbits;hence,theeffectivedatarateishalved.I.e.totransmitatthesameeffectivedataratewhenusingFEC,itisnecessarytousetwiceashighover-the-airdatarate.Thiswillrequireahigherreceiverbandwidth,andthusreducesensitivity.Inotherwords,theimprovedreceptionbyusingFECandthedegradedsensitivityfromahigherreceiverbandwidthwillbecounteractingfactors.18.2

Interleaving

PER1(1BER)packet_length

alowerBERcanbeusedtoallowlongerpackets,orahigherpercentageofpacketsofagivenlength,tobetransmittedsuccessfully.Finally,inrealisticISMradioenvironments,transientandtime-varyingphenomenawill

SWRS040C

Datareceivedthroughradiochannelswilloftenexperiencebursterrorsdueto

Page37of

CC2500interferenceandtime-varyingsignalstrengths.Inordertoincreasetherobustnesstoerrorsspanningmultiplebits,interleavingisusedwhenFECisenabled.Afterde-interleaving,acontinuousspanoferrorsinthereceivedstreamwillbecomesingleerrorsspreadapart.

WhenFECandinterleavingisusedatleastoneextrabyteisrequiredfortrellistermination.Inaddition,theamountofdatatransmittedovertheairmustbeamultipleofthesizeoftheinterleaverbuffer(twobytes).Thepacketcontrolhardwarethereforeautomaticallyinsertsoneortwoextrabytesattheendofthepacket,sothatthetotallengthofthedatatobeinterleavedisanevennumber.Notethattheseextrabytesareinvisibletotheuser,astheyareremovedbeforethereceivedpacketenterstheRXFIFO.

WhenFECandinterleavingisusedtheminimumdatapayloadis2bytes.

CC2500employsmatrixinterleaving,whichisillustratedinFigure14.Theon-chipinterleavingandde-interleavingbuffersare4x4matrices.Inthetransmitter,thedatabitsfromtherate½convolutionalcoderarewrittenintotherowsofthematrix,whereasthebitsequencetobetransmittedisreadfromthecolumnsofthematrix.Conversely,inthereceiver,thereceivedsymbolsarewrittenintotherowsofthematrix,whereasthedatapassedontotheconvolutionaldecoderisreadfromthecolumnsofthematrix.

InterleaverWritebufferInterleaverReadbufferPacketEngineFECEncoderModulatorInterleaverWritebufferInterleaverReadbufferDemodulatorFECDecoderPacketEngineFigure14:GeneralPrincipleofMatrixInterleaving

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CC250019RadioControl

CC2500hasabuilt-instatemachinethatisusedtoswitchbetweendifferentoperationstates(modes).ThechangeofstateisdoneeitherbyusingcommandstrobesorbyinternaleventssuchasTXFIFOunderflow.

Asimplifiedstatediagram,togetherwithtypicalusageandcurrentconsumption,isshowninFigure5onpage15.ThecompleteradiocontrolstatediagramisshowninFigure15.Thenumbersrefertothestatenumber

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readableintheMARCSTATEstatusregister.Thisregisterisprimarilyfortestpurposes.19.1

Power-OnStart-UpSequence

Whenthepowersupplyisturnedon,thesystemmustbereset.Oneofthefollowingtwosequencesmustbefollowed:Automaticpower-onreset(POR)ormanualreset.

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19.1.1AutomaticPOR

Apower-onresetcircuitisincludedintheCC2500.TheminimumrequirementsstatedinSection4.9mustbefollowedforthepower-onresettofunctionproperly.Theinternalpower-upsequenceiscompletedwhenCHIP_RDYngoeslow.CHIP_RDYnisobservedontheSOpinafterCSnispulledlow.SeeSection10.1formoredetailsonCHIP_RDYn.

WhentheCC2500resetiscompletedthechipwillbeintheIDLEstateandthecrystaloscillatorwillberunning.Ifthechiphashadsufficienttimeforthecrystaloscillatortostabilizeafterthepower-on-reset,theSOpinwillgolowimmediatelyaftertakingCSnlow.IfCSnistakenlowbeforeresetiscompletedtheSOpinwillfirstgohigh,indicatingthatthecrystaloscillatorisnotstabilized,beforegoinglowasshowninFigure16.

SWRS040CCC2500Page40of

CC2500oscillatorandmakethechipentertheIDLEstate.

Whenwakeonradioisenabled,theWORmodulewillcontrolthevoltageregulatorasdescribedinSection19.5.19.4

ActiveModes

hasbeensuccessfullytransmitted.ThenthestatewillchangeasindicatedbytheMCSM1.TXOFF_MODEsetting.ThepossibledestinationsarethesameasforRX.

TheMCUcanmanuallychangethestatefromRXtoTXandviceversabyusingthecommandstrobes.IftheradiocontrolleriscurrentlyintransmitandtheSRXstrobeisused,thecurrenttransmissionwillbeendedandthetransitiontoRXwillbedone.

IftheradiocontrollerisinRXwhentheSTXorSFSTXONcommandstrobesareused,theTX-if-CCAfunctionwillbeused.Ifthechannelisnotclear,thechipwillremaininRX.TheMCSM1.CCA_MODEsettingcontrolstheconditionsforclearchannelassessment.SeeSection17.5onpage37fordetails.

TheSIDLEcommandstrobecanalwaysbeusedtoforcetheradiocontrollertogototheIDLEstate.19.5

WakeOnRadio(WOR)

CC2500hastwoactivemodes:receiveandtransmit.ThesemodesareactivateddirectlybytheMCUbyusingtheSRXandSTXcommandstrobes,orautomaticallybyWakeonRadio.

Thefrequencysynthesizermustbecalibratedregularly.CC2500hasonemanualcalibrationoption(usingtheSCALstrobe),andthreeautomaticcalibrationoptions,controlledbytheMCSM0.FS_AUTOCALsetting:

CalibratewhengoingfromIDLEtoeitherRXorTX(orFSTXON)

CalibratewhengoingfromeitherRXorTXtoIDLEautomatically

CalibrateeveryfourthtimewhengoingfromeitherRXorTXtoIDLEautomatically

TheoptionalWakeonRadio(WOR)functionalityenablesCC2500toperiodicallywakeupfromSLEEPandlistenforincomingpacketswithoutMCUinteraction.

WhentheSWORstrobecommandissentontheSPIinterface,theCC2500willgototheSLEEPstatewhenCSnisreleased.TheRCoscillatormustbeenabledbeforetheWORstrobecanbeused,asitistheclocksourcefortheWORtimer.Theon-chiptimerwillsetCC2500intotheIDLEstateandthentheRXstate.AfteraprogrammabletimeinRX,thechipgoesbacktotheSLEEPstate,unlessapacketisreceived.SeeFigure18andSection19.7fordetailsonhowthetimeoutworks.SettheCC2500intotheIDLEstatetoexitWORmode.

IftheradiogoesfromTXorRXtoIDLEbyissuinganSIDLEstrobe,calibrationwillnotbeperformed.ThecalibrationtakesaconstantnumberofXOSCcycles(seeTable28fortimingdetails).

WhenRXisactivated,thechipwillremaininreceivemodeuntilapacketissuccessfullyreceivedortheRXterminationtimerexpires(seeSection19.7).Note:theprobabilitythatafalsesyncwordisdetectedcanbereducedbyusingPQT,CS,maximumsyncwordlengthandsyncwordqualifiermodeasdescribeinSection17.AfterapacketissuccessfullyreceivedtheradiocontrollerwillthengotothestateindicatedbytheMCSM1.RXOFF_MODEsetting.Thepossibledestinationsare:

IDLE

FSTXON:FrequencysynthesizeronandreadyattheTXfrequency.ActivateTXwithSTX.

TX:StartsendingpreamblesRX:Startsearchforanewpacket



CC2500canbesetuptosignaltheMCUthatapackethasbeenreceivedbyusingtheGDOpins.Ifapacketisreceived,theMCSM1.RXOFF_MODEwilldeterminethebehaviourattheendofthereceivedpacket.WhentheMCUhasreadthepacket,itcanputthechipbackintoSLEEPwiththeSWORstrobefromtheIDLEstate.TheFIFOwillloseitscontentsintheSLEEPstate.

TheWORtimerhastwoevents,Event0andEvent1.IntheSLEEPstatewithWORactivated,reachingEvent0willturnonthedigitalregulatorandstartthecrystaloscillator.

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Similarly,whenTXisactivethechipwillremainintheTXstateuntilthecurrentpacket

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CC2500Event1followsEvent0afteraprogrammedtimeout.

ThetimebetweentwoconsecutiveEvent0isprogrammedwithamantissavaluegivenbyWOREVT1.EVENT0andWOREVT0.EVENT0,andanexponentvaluesetbyWORCTRL.WOR_RES.Theequationis:

clock.WhenthechipgoestotheSLEEPstate,theRCoscillatorwillusethelastvalidcalibrationresult.ThefrequencyoftheRCoscillatorislockedtothemaincrystalfrequencydividedby750.

Inapplicationswheretheradiowakesupveryoften,typicallyseveraltimeseverysecond,itispossibletodotheRCoscillatorcalibrationonceandthenturnoffcalibration(WORCTRL.RC_CAL=0)toreducethecurrentconsumption.ThisrequiresthatRCoscillatorcalibrationvaluesarereadfromregistersRCCTRL0_STATUSandRCCTRL1_STATUSandwrittenbacktoRCCTRL0andRCCTRL0respectively.IftheRCoscillatorcalibrationisturnedoffitwillhavetobemanuallyturnedonagainiftemperatureandsupplyvoltagechanges.

RefertoApplicationNoteAN047[3]forfurtherdetails.19.6

Timing

tEvent0

750

EVENT025WOR_RES

fXOSC

TheEvent1timeoutisprogrammedwithWORCTRL.EVENT1.Figure18showsthetimingrelationshipbetweenEvent0timeoutandEvent1timeout.

Figure18:Event0andEvent1RelationshipThetimefromtheCC2500entersSLEEPstateuntilthenextEvent0isprogrammedtoappear(tSLEEPinFigure18)shouldbelargerthan11.08mswhenusinga26MHzcrystaland10.67mswhena27MHzcrystalisused.IftSLEEPislessthan11.08(10.67)msthereisachancethattheconsecutiveEvent0willoccur

TheradiocontrollercontrolsmosttiminginCC2500,suchassynthesizercalibration,PLLlocktimeandRX/TXturnaroundtimes.TimingfromIDLEtoRXandIDLEtoTXisconstant,dependentontheautocalibrationsetting.RX/TXandTX/RXturnaroundtimesareconstant.Thecalibrationtimeisconstant18739clockperiods.Table28showstimingincrystalclockcyclesforkeystatetransitions.PowerontimeandXOSCstart-uptimesarevariable,butwithinthelimitsstatedinTable7.Notethatinafrequencyhoppingspreadspectrumoramulti-channelprotocolthecalibrationtimecanbereducedfrom721µstoapproximately150µs.ThisisexplainedinSection31.2.

Description

IDLEtoRX,nocalibrationIDLEtoRX,withcalibrationIDLEtoTX/FSTXON,nocalibrationIDLEtoTX/FSTXON,withcalibrationTXtoRXswitchRXtoTXswitch

RXorTXtoIDLE,nocalibrationRXorTXtoIDLE,withcalibrationManualcalibration

XOSCPeriods2298~210372298~210375602502~18739~18739

26MHzCrystal88.4μs809μs88.4μs809μs21.5μs9.6μs0.1μs721μs721μs

750

128secondsfXOSC

tooearly.ApplicationNoteAN047[3]explainsindetailthetheoryofoperationandthedifferentregistersinvolvedwhenusingWOR,aswellashighlightingimportantaspectswhenusingWORmode.

19.5.1RCOscillatorandTiming

Thefrequencyofthelow-powerRCoscillatorusedfortheWORfunctionalityvarieswithtemperatureandsupplyvoltage.Inordertokeepthefrequencyasaccurateaspossible,theRCoscillatorwillbecalibratedwheneverpossible,whichiswhentheXOSCisrunningandthechipisnotintheSLEEPstate.WhenthepowerandXOSCisenabled,theclockusedbytheWORtimerisadividedXOSC

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Table28:StateTransitionTiming

Page42of

CC250019.7

RXTerminationTimer

CC2500hasoptionalfunctionsforautomaticterminationofRXafteraprogrammabletime.Themainuseforthisfunctionalityiswake-on-radio(WOR),butitmaybeusefulforotherapplications.TheterminationtimerstartswheninRXstate.ThetimeoutisprogrammablewiththeMCSM2.RX_TIMEsetting.Whenthetimerexpires,theradiocontrollerwillchecktheconditionforstayinginRX;iftheconditionisnotmet,RXwillterminate.

Theprogrammableconditionsare:

MCSM2.RX_TIME_QUAL=0:ContinuereceiveifsyncwordhasbeenfoundMCSM2.RX_TIME_QUAL=1:Continuereceiveifsyncwordhasbeenfoundorpreamblequalityisabovethreshold(PQT)

ForOOKmodulation,lackofcarriersenseisonlyconsideredvalidaftereightsymbolperiods.Thus,theMCSM2.RX_TIME_RSSIfunctioncanbeusedinOOKmodewhenthedistancebetween“1”symbolsis8orless.IfRXterminatesduetonocarriersensewhentheMCSM2.RX_TIME_RSSIfunctionisused,orifnosyncwordwasfoundwhenusingtheMCSM2.RX_TIMEtimeoutfunction,thechipwillalwaysgobacktoIDLEifWORisdisabledandbacktoSLEEPifWORisenabled.Otherwise,theMCSM1.RXOFF_MODEsettingdeterminesthestatetogotowhenRXends.ThismeansthatthechipwillnotautomaticallygobacktoSLEEPonceasyncwordhasbeenreceived.ItisthereforerecommendedtoalwayswakeupthemicrocontrolleronsyncworddetectionwhenusingWORmode.Thiscanbedonebyselectingoutputsignal6(seeTable33onpage53)ononeoftheprogrammableGDOoutputpins,andprogrammingthemicrocontrollertowakeuponanedge-triggeredinterruptfromthisGDOpin.

Ifthesystemcanexpectthetransmissiontohavestartedwhenenablingthereceiver,theMCSM2.RX_TIME_RSSIfunctioncanbeused.TheradiocontrollerwillthenterminateRXifthefirstvalidcarriersensesampleindicatesnocarrier(RSSIbelowthreshold).SeeSection17.4onpage35fordetailsonCarrierSense.

20DataFIFO

TheCC2500containstwobyteFIFOs,oneforreceiveddataandonefordatatobetransmitted.TheSPIinterfaceisusedtoreadfromtheRXFIFOandwritetotheTXFIFO.Section10.5containsdetailsontheSPIFIFOaccess.TheFIFOcontrollerwilldetectoverflowintheRXFIFOandunderflowintheTXFIFO.

WhenwritingtotheTXFIFOitistheresponsibilityoftheMCUtoavoidTXFIFOoverflow.ATXFIFOoverflowwillresultinanerrorintheTXFIFOcontent.

Likewise,whenreadingtheRXFIFOtheMCUmustavoidreadingtheRXFIFOpastitsemptyvalue,sinceanRXFIFOunderflowwillresultinanerrorinthedatareadoutoftheRXFIFO.

ThechipstatusbytethatisavailableontheSOpinwhiletransferringtheSPIheadercontainsthefillgradeoftheRXFIFOiftheaccessisareadoperationandthefillgradeoftheTXFIFOiftheaccessisawriteoperation.Section10.1onpage22containsmoredetailsonthis.

SWRS040C

ThenumberofbytesintheRXFIFOandTXFIFOcanalsobereadfromthestatusregistersRXBYTES.NUM_RXBYTESandTXBYTES.NUM_TXBYTESrespectively.IfareceiveddatabyteiswrittentotheRXFIFOattheexactsametimeasthelastbyteintheRXFIFOisreadovertheSPIinterface,theRXFIFOpointerisnotproperlyupdatedandthelastreadbyteisduplicated.ToavoidthisproblemoneshouldneveremptytheRXFIFObeforethelastbyteofthepacketisreceived.ForpacketlengthslessthanbytesitisrecommendedtowaituntilthecompletepackethasbeenreceivedbeforereadingitoutoftheRXFIFO.

IfthepacketlengthislargerthanbytestheMCUmustdeterminehowmanybytescanbereadfromtheRXFIFO(RXBYTES.NUM_RXBYTES-1)andthefollowingsoftwareroutinecanbeused:

Page43of

CC25001.Read

RXBYTES.NUM_RXBYTES

repeatedlyatarateguaranteedtobeatleasttwicethatofwhichRFbytesarereceiveduntilthesamevalueisreturnedtwice;storevalueinn.

FIFO_THR0(0000)1(0001)2(0010)3(0011)4(0100)5(0101)6(0110)7(0111)8(1000)9(1001)10(1010)11(1011)12(1100)13(1101)14(1110)15(1111)

BytesinTXFIFO

615753494137332925211713951

BytesinRXFIFO

48121620242832304448525660

2.Ifn<#ofbytesremaininginpacket,read

n-1bytesfromtheRXFIFO.3.Repeatsteps1and2untiln=#ofbytes

remaininginthepacket.4.ReadtheremainingbytesfromtheRX

FIFO.The4-bitFIFOTHR.FIFO_THRsettingisusedtoprogramthresholdpointsintheFIFOs.Table29liststhe16FIFO_THRsettingsandthecorrespondingthresholdsfortheRXandTXFIFOs.ThethresholdvalueiscodedinoppositedirectionsfortheRXFIFOandTXFIFO.Thisgivesequalmargintotheoverflowandunderflowconditionswhenthethresholdisreached.

AsignalwillassertwhenthenumberofbytesintheFIFOisequaltoorhigherthantheprogrammedthreshold.ThesignalcanbeviewedontheGDOpins(seeSection28onpage51).

Figure20showsthenumberofbytesinboththeRXFIFOandTXFIFOwhenthethresholdflagtoggles,inthecaseofFIFO_THR=13.Figure19showsthesignalastherespectiveFIFOisfilledabovethethreshold,andthendrainedbelow.

NUM_RXBYTES

GDO

Table29:FIFO_THRSettingsandtheCorrespondingFIFOThresholds

OverflowmarginFIFO_THR=1356bytes53555657565553FIFO_THR=13Underflowmargin8bytesTXFIFO

NUM_TXBYTES

GDO

67109876RXFIFO

Figure19:FIFO_THR=13vs.NumberofBytesinFIFO(GDOx_CFG=0x00inRXand

GDOx_CFG=0x02inTX)

Figure20:ExampleofFIFOsatThreshold

21FrequencyProgramming

ThefrequencyprogramminginCC2500isdesignedtominimizetheprogrammingneededinachannel-orientedsystem.

Tosetupasystemwithchannelnumbers,thedesiredchannelspacingisprogrammedwiththeMDMCFG0.CHANSPC_Mand

SWRS040C

MDMCFG1.CHANSPC_Eregisters.Thechannel

spacingregistersaremantissaandexponentrespectively.

Thebaseorstartfrequencyissetbythe24bitfrequencywordlocatedintheFREQ2,FREQ1andFREQ0registers.Thiswordwilltypically

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CC2500besettothecentreofthelowestchannelfrequencythatistobeused.

Thedesiredchannelnumberisprogrammedwiththe8-bitchannelnumberregister,

CHANNR.CHAN,whichismultipliedbythechanneloffset.Theresultantcarrierfrequencyisgivenby:

fcarrier

fXOSC

FREQCHAN256CHANSPC_M2CHANSPC_E2162

Witha26MHzcrystalthemaximumchannelspacingis405kHz.Togete.g.1MHzchannelspacingonesolutionistouse333kHzchannelspacingandselecteachthirdchannelinCHANNR.CHAN.

ThepreferredIFfrequencyisprogrammedwiththeFSCTRL1.FREQ_IFregister.TheIFfrequencyisgivenby:

NotethattheSmartRFStudiosoftware[5]automaticallycalculatestheoptimumFSCTRL1.FREQ_IFregistersettingbasedonchannelspacingandchannelfilterbandwidth.Ifanyfrequencyprogrammingregisterisalteredwhenthefrequencysynthesizerisrunning,thesynthesizermaygiveanundesiredresponse.Hence,thefrequencyprogrammingshouldonlybeupdatedwhentheradioisintheIDLEstate.

fIF

fXOSC

FREQ_IF210

22VCO

TheVCOiscompletelyintegratedon-chip.22.1

VCOandPLLSelf-Calibration

NotethatthecalibrationvaluesaremaintainedinSLEEPmode,sothecalibrationisstillvalidafterwakingupfromSLEEPmode(unlesssupplyvoltageortemperaturehaschangedsignificantly).

TocheckthatthePLLisinlocktheusercanprogramregisterIOCFGx.GDOx_CFGto0x0AandusethelockdetectoroutputavailableontheGDOxpinasaninterruptfortheMCU(x=0,1or2).ApositivetransitionontheGDOxpinmeansthatthePLLisinlock.AsanalternativetheusercanreadregisterFSCAL1.ThePLLisinlockiftheregistercontentisdifferentfrom0x3F.ReferalsototheCC2500ErrataNotes[1].FormorerobustoperationthesourcecodecouldincludeachecksothatthePLLisre-calibrateduntilPLLlockisachievedifthePLLdoesnotlockthefirsttime.

TheVCOcharacteristicswillvarywithtemperatureandsupplyvoltagechanges,aswellasthedesiredoperatingfrequency.Inordertoensurereliableoperation,CC2500includesfrequencysynthesizerself-calibrationcircuitry.Thiscalibrationshouldbedoneregularly,andmustbeperformedafterturningonpowerandbeforeusinganewfrequency(orchannel).ThenumberofXOSCcyclesforcompletingthePLLcalibrationisgiveninTable28onpage42.

Thecalibrationcanbeinitiatedautomaticallyormanually.Thesynthesizercanbeautomaticallycalibratedeachtimethesynthesizeristurnedon,oreachtimethesynthesizeristurnedoffautomatically.ThisisconfiguredwiththeMCSM0.FS_AUTOCALregistersetting.Inmanualmode,thecalibrationisinitiatedwhentheSCALcommandstrobeisactivatedintheIDLEmode.

SWRS040CPage45of

CC250023VoltageRegulators

CC2500containsseveralon-chiplinearvoltageregulators,whichgeneratethesupplyvoltageneededbylow-voltagemodules.Thesevoltageregulatorsareinvisibletotheuser,andcanbeviewedasintegralpartsofthevariousmodules.TheusermusthowevermakesurethattheabsolutemaximumratingsandrequiredpinvoltagesinTable1andTable13arenotexceeded.Thevoltageregulatorforthedigitalcorerequiresoneexternaldecouplingcapacitor.

SettingtheCSnpinlowturnsonthevoltageregulatortothedigitalcoreandstartsthecrystaloscillator.TheSOpinontheSPIinterfacemustgolowbeforethefirstpositiveedgeofSCLK(setuptimeisgiveninTable16).

Ifthechipisprogrammedtoenterpower-downmode,(SPWDstrobeissued),thepowerwillbeturnedoffafterCSngoeshigh.ThepowerandcrystaloscillatorwillbeturnedonagainwhenCSngoeslow.

ThevoltageregulatoroutputshouldonlybeusedfordrivingtheCC2500.

24OutputPowerProgramming

TheRFoutputpowerlevelfromthedevicehastwolevelsofprogrammability,asillustratedinFigure21.

TheRFoutputpowerlevelfromthedeviceisprogrammedthroughthePATABLEregister.

If2-FSK,GFSKorMSKmodulationisusedthedesiredoutputpowerisprogrammedtoindex0inthePATABLEregister(PATABLE(0)[7:0]).The3-bitFREND0.PA_POWERvalueshallbesetto0(resetdefaultvalue).

IfOOKmodulationisusedthedesiredoutputpowerforthelogic0andlogic1powerlevelsareprogrammedtoindex0andindex1inthePATABLEregisterrespectively(PATABLE(0)[7:0]andPATABLE(1)[7:0]).The3-bit

FREND0.PA_POWERvalueshallbesetto

Table31containsrecommendedPATABLEsettingsforvariousoutputlevelsandfrequencybands.SeeSection10.6onpage24forPATABLEprogrammingdetails.TheSmartRFStudiosoftware[5]shouldbeusedtoobtainoptimumPATABLEsettingsforvariousoutputpowers.

PATABLEmustbeprogrammedinburstmodeifwritingtootherentriesthanPATABLE(0)(OOKmodulation).NotethatallcontentofthePATABLE,exceptforthefirstbyte(index0)islostwhenenteringtheSLEEPstate.



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CC2500SWRS040CPage47of

CC250025Selectivity

Figure22toFigure26showthetypicalselectivityperformance(adjacentandalternaterejection).

504030]Bd[ytiv20itceleS100-1-0.8-0.6-0.4-0.200.20.40.60.81-10Frequencyoffset[MHz]Figure22:TypicalSelectivityat2.4kBaud.IFFrequencyis273.9kHz.

MDMCFG2.DEM_DCFILT_OFF=1

40353025]B20d[ytiv15itceleS1050-1-0.8-0.6-0.4-0.200.20.40.60.81-5-10Frequencyoffset[MHz]Figure23:TypicalSelectivityat10kBaud.IFFrequencyis273.9kHz.

MDMCFG2.DEM_DCFILT_OFF=1

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CC2500504030]Bd20[ytivitcele10S0-3-2-10123-10-20Frequencyoffset[MHz]Figure24:TypicalSelectivityat250kBaud.IFFrequencyis177.7kHz.

MDMCFG2.DEM_DCFILT_OFF=0

504030]Bd20[ytivitcel10eS0-3-2-10123-10-20Frequencyoffset[MHz]Figure25:TypicalSelectivityat250kBaud.IFFrequencyis457kHz.

MDMCFG2.DEM_DCFILT_OFF=1

3530252015]Bd[y10tivitc5eleS0-3-2-10123-5-10-15-20Frequencyoffset[MHz]Figure26:TypicalSelectivityat500kBaud.IFFrequencyis304.7kHz.

MDMCFG2.DEM_DCFILT_OFF=0

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CC250026CrystalOscillator

Acrystalinthefrequencyrange26-27MHzmustbeconnectedbetweentheXOSC_Q1andXOSC_Q2pins.Theoscillatorisdesignedforparallelmodeoperationofthecrystal.Inaddition,loadingcapacitors(C81andC101)forthecrystalarerequired.Theloadingcapacitorvaluesdependonthetotalloadcapacitance,CL,specifiedforthecrystal.ThetotalloadcapacitanceseenbetweenthecrystalterminalsshouldequalCLforthecrystaltooscillateatthespecifiedfrequency.

ThecrystaloscillatorcircuitisshowninFigure27.TypicalcomponentvaluesfordifferentvaluesofCLaregiveninTable32.

Thecrystaloscillatorisamplituderegulated.Thismeansthatahighcurrentisusedtostartuptheoscillations.Whentheamplitudebuildsup,thecurrentisreducedtowhatisnecessarytomaintainapproximately0.4Vppsignalswing.Thisensuresafaststart-up,andkeepsthedriveleveltoaminimum.TheESRofthecrystalshouldbewithinthespecificationinordertoensureareliablestart-up(seeSection4.4onpage12).

XOSC_Q1XOSC_Q2CL

111C81C101

Cparasitic

TheparasiticcapacitanceisconstitutedbypininputcapacitanceandPCBstraycapacitance.Totalparasiticcapacitanceistypically2.5pF.

XTALC81C101Figure27:CrystalOscillatorCircuit

ComponentC81C101

CL=10pF15pF15pF

CL=13Pf22pF22pF

CL=16pF27pF27pF

Table32:CrystalOscillatorComponentValues

26.1

ReferenceSignal

Thechipcanalternativelybeoperatedwithareferencesignalfrom26to27MHzinsteadofacrystal.Thisinputclockcaneitherbeafull-swingdigitalsignal(0VtoVDD)orasinewaveofmaximum1Vpeak-peakamplitude.Thereferencesignalmustbeconnectedtothe

XOSC_Q1input.ThesinewavemustbeconnectedtoXOSC_Q1usingaserialcapacitor.Whenusingafull-swingdigitalsignalthiscapacitorcanbeomitted.TheXOSC_Q2linemustbeleftun-connected.C81andC101canbeomittedwhenusingareferencesignal.

27ExternalRFMatch

ThebalancedRFinputandoutputofCC2500sharetwocommonpinsandaredesignedforasimple,low-costmatchingandbalunnetworkontheprintedcircuitboard.Thereceive-andtransmitswitchingattheCC2500front-endiscontrolledbyadedicatedon-chipfunction,eliminatingtheneedforanexternalRX/TX-switch.

AfewpassiveexternalcomponentscombinedwiththeinternalRX/TXswitch/termination

SWRS040C

circuitryensuresmatchinbothRXandTXmode.

AlthoughCC2500hasabalancedRFinput/output,thechipcanbeconnectedtoasingle-endedantennawithfewexternallowcostcapacitorsandinductors.

Thepassivematching/filteringnetworkconnectedtoCC2500shouldhavethefollowingdifferentialimpedanceasseenfromtheRF-port(RF_PandRF_N)towardstheantenna:

Page50of

CC2500Zout=80+j74Ω

ToensureoptimalmatchingoftheCC2500differentialoutputitishighlyrecommendedto

followtheCC2500EMreferencedesigns[4]ascloselyaspossible.GerberfilesforthereferencedesignsareavailablefordownloadfromtheTIwebsite.

28PCBLayoutRecommendations

Thetoplayershouldbeusedforsignalrouting,andtheopenareasshouldbefilledwithmetallizationconnectedtogroundusingseveralvias.

Theareaunderthechipisusedforgroundingandshallbeconnectedtothebottomgroundplanewithseveralviasforgoodthermalperformanceandsufficientlylowinductancetoground.IntheCC2500EMreferencedesigns[4]5viasareplacedinsidetheexposeddieattachedpad.Theseviasshouldbe“tented”(coveredwithsoldermask)onthecomponentsideofthePCBtoavoidmigrationofsolderthroughtheviasduringthesolderreflowprocess.

Thesolderpastecoverageshouldnotbe100%.Ifitis,outgassingmayoccurduringthereflowprocess,whichmaycausedefects(splattering,solderballing).Using“tented”viasreducesthesolderpastecoveragebelow100%.

SeeFigure28fortopsolderresistandtoppastemasks.SeeFigure30forrecommendedPCBlayoutforQLP20package.

Eachdecouplingcapacitorshouldbeplacedascloseaspossibletothesupplypinitissupposedtodecouple.Eachdecoupling

capacitorshouldbeconnectedtothepowerlinebyseparatevias.ThebestroutingisfromthepowerlinetothedecouplingcapacitorandthentotheCC2500supplypin.Supplypowerfilteringisveryimportant.

Eachdecouplingcapacitorgroundpadshouldbeconnectedtothegroundplaneusingaseparatevia.Directconnectionsbetweenneighboringpowerpinswillincreasenoisecouplingandshouldbeavoidedunlessabsolutelynecessary.

Theexternalcomponentsshouldideallybeassmallaspossible(0402isrecommended)andsurfacemountdevicesarehighlyrecommended.Pleasenotethatcomponentssmallerthanthosespecifiedmayhavedifferingcharacteristics.

PrecautionshouldbeusedwhenplacingthemicrocontrollerinordertoavoidnoiseinterferingwiththeRFcircuitry.

ACC2500/2550DKDevelopmentKitwithafullyassembledCC2500EMEvaluationModuleisavailable.Itisstronglyadvisedthatthisreferencelayoutisfollowedverycloselyinordertogetthebestperformance.Theschematic,BOMandlayoutGerberfilesareallavailablefromtheTIwebsite[4].

Figure28:Left:TopSolderResistMask(negative).Right:TopPasteMask.CirclesareVias.

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CC250029GeneralPurpose/TestOutputControlPins

ThethreedigitaloutputpinsGDO0,GDO1andGDO2aregeneralcontrolpinsconfiguredwithIOCFG0.GDO0_CFG,IOCFG1.GDO1_CFGandIOCFG2.GDO2_CFGrespectively.Table33showsthedifferentsignalsthatcanbemonitoredontheGDOpins.ThesesignalscanbeusedasinputstotheMCU.GDO1isthesamepinastheSOpinontheSPIinterface,thustheoutputprogrammedonthispinwillonlybevalidwhenCSnishigh.ThedefaultvalueforGDO1is3-stated,whichisusefulwhentheSPIinterfaceissharedwithotherdevices.

ThedefaultvalueforGDO0isa135-141kHzclockoutput(XOSCfrequencydividedby192).SincetheXOSCisturnedonatpower-on-reset,thiscanbeusedtoclocktheMCUinsystemswithonlyonecrystal.WhentheMCUisupandrunning,itcanchangetheclockfrequencybywritingtoIOCFG0.GDO0_CFG.Anon-chipanalogtemperaturesensorisenabledbywritingthevalue128(0x80)tothe

IOCFG0.GDO0_CFGregister.ThevoltageontheGDO0pinisthenproportionaltotemperature.SeeSection4.7onpage14fortemperaturesensorspecifications.

IftheIOCFGx.GDO0_CFGsettingislessthan0x20andIOCFGx_GDOx_INVis0(1),theGDO0andGDO2pinswillbehardwiredto0(1)andtheGDO1pinwillbehardwiredto1(0)intheSLEEPstate.ThesesignalswillbehardwireduntiltheCHIP_RDYnsignalgoeslow.

IftheIOCFGx.GDO0_CFGsettingis0x20orhighertheGDOpinswillworkasprogrammedalsoinSLEEPstate.Asanexample,GDO1ishighimpedanceinallstatesifIOCFG1.GDO0_CFG=0x2E.

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CC2500GDOx_CFG[5:0]]0(0x00)1(0x01)2(0x02)3(0x03)4(0x04)5(0x05)6(0x06)7(0x07)8(0x08)9(0x09)10(0x0A)11(0x0B)12(0x0C)13(0x0D)14(0x0E)15(0x0F)16(0x10)to21(0x15)22(0x16)23(0x17)24(0x18)25(0x19)26(0x1A)27(0x1B)28(0x1C)29(0x1D)30(0x1E)to35(0x23)36(0x24)37(0x25)38(0x26)39(0x27)40(0x28)41(0x29)42(0x2A)43(0x2B)44(0x2C)45(0x2D)46(0x2E)47(0x2F)48(0x30)49(0x31)50(0x32)51(0x33)52(0x34)53(0x35)(0x36)55(0x37)56(0x38)57(0x39)58(0x3A)59(0x3B)60(0x3C)61(0x3D)62(0x3E)63(0x3F)DescriptionAssociatedtotheRXFIFO:AssertswhenRXFIFOisfilledatorabovetheRXFIFOthreshold.De-assertswhenRXFIFOisdrainedbelowthesamethreshold.

AssociatedtotheRXFIFO:AssertswhenRXFIFOisfilledatorabovetheRXFIFOthresholdortheendofpacketisreached.De-assertswhentheRXFIFOisempty.

AssociatedtotheTXFIFO:AssertswhentheTXFIFOisfilledatorabovetheTXFIFOthreshold.De-assertswhentheTXFIFOisbelowthesamethreshold.

AssociatedtotheTXFIFO:AssertswhenTXFIFOisfull.De-assertswhentheTXFIFOisdrainedbelowtheTXFIFOthreshold.

AssertswhentheRXFIFOhasoverflowed.De-assertswhentheFIFOhasbeenflushed.AssertswhentheTXFIFOhasunderflowed.De-assertswhentheFIFOisflushed.Assertswhensyncwordhasbeensent/received,andde-assertsattheendofthepacket.InRX,thepinwillde-assertwhentheoptionaladdresscheckfailsortheRXFIFOoverflows.InTXthepinwillde-assertiftheTXFIFOunderflows.AssertswhenapackethasbeenreceivedwithCRCOK.De-assertswhenthefirstbyteisreadfromtheRXFIFO.OnlyvalidifPKTCTRL0.CC2400_EN=1.

PreambleQualityReached.AssertswhenthePQIisabovetheprogrammedPQTvalue.Clearchannelassessment.HighwhenRSSIlevelisbelowthreshold(dependentonthecurrentCCA_MODEsetting)Lockdetectoroutput.ThePLLisinlockifthelockdetectoroutputhasapositivetransitionorisconstantlylogichigh.TocheckforPLLlockthelockdetectoroutputshouldbeusedasaninterruptfortheMCU.SerialClock.Synchronoustothedatainsynchronousserialmode.InRXmode,dataissetuponthefallingedgebyCC2500whenGDOx_INV=0.

InTXmode,dataissampledbyCC2500ontherisingedgeoftheserialclockwhenGDOx_INV=0.SerialSynchronousDataOutput(DO).Usedforsynchronousserialmode.SerialDataOutput.Usedforasynchronousserialmode.Carriersense.HighifRSSIlevelisabovethreshold.CRC_OK.ThelastCRCcomparisonmatched.Clearedwhenentering/restartingRXmode.OnlyvalidifPKTCTRL0.CC2400_EN=1.Reserved–usedfortest.

RX_HARD_DATA[1].CanbeusedtogetherwithRX_SYMBOL_TICKforalternativeserialRXoutput.RX_HARD_DATA[0].CanbeusedtogetherwithRX_SYMBOL_TICKforalternativeserialRXoutput.Reserved–usedfortest.Reserved–usedfortest.Reserved–usedfortest.PA_PD.Note:PA_PDwillhavethesamesignallevelinSLEEPandTXstates.TocontrolanexternalPAorRX/TXswitchinapplicationswheretheSLEEPstateisuseditisrecommendedtouseGDOx_CFGx=0x2Finstead.

LNA_PD.Note:LNA_PDwillhavethesamesignallevelinSLEEPandRXstates.TocontrolanexternalLNAorRX/TXswitchinapplicationswheretheSLEEPstateisuseditisrecommendedtouseGDOx_CFGx=0x2Finstead.RX_SYMBOL_TICK.CanbeusedtogetherwithRX_HARD_DATAforalternativeserialRXoutput.Reserved–usedfortest.

WOR_EVNT0WOR_EVNT1Reserved–usedfortest.CLK_32kReserved–usedfortest.CHIP_RDYnReserved–usedfortest.XOSC_STABLEReserved–usedfortest.GDO0_Z_EN_N.Whenthisoutputis0,GDO0isconfiguredasinput(forserialTXdata).Highimpedance(3-state)HWto0(HW1achievedbysettingGDOx_INV=1).CanbeusedtocontrolanexternalLNA/PAorRX/TXswitch.CLK_XOSC/1CLK_XOSC/1.5CLK_XOSC/2CLK_XOSC/3CLK_XOSC/4CLK_XOSC/6CLK_XOSC/8Note:Thereare3GDOpins,butonlyoneCLK_XOSC/ncanbeselectedasanoutputatanyCLK_XOSC/12time.IfCLK_XOSC/nistobemonitoredononeoftheGDOpins,theothertwoGDOpinsmust

beconfiguredtovalueslessthan0x30.TheGDO0defaultvalueisCLK_XOSC/192.CLK_XOSC/16CLK_XOSC/24CLK_XOSC/32CLK_XOSC/48CLK_XOSC/CLK_XOSC/96CLK_XOSC/128CLK_XOSC/192Table33:GDOxSignalSelection(x=0,1or2)

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CC250030AsynchronousandSynchronousSerialOperation

SeveralfeaturesandmodesofoperationhavebeenincludedintheCC2500toprovidebackwardcompatibilitywithpreviousChipconproductsandotherexistingRFcommunicationsystems.Fornewsystems,itisrecommendedtousethebuilt-inpackethandlingfeatures,astheycangivemorerobustcommunication,significantlyoffloadthemicrocontrollerandsimplifysoftwaredevelopment.30.1

AsynchronousOperation

30.2

SynchronousSerialOperation

ForbackwardcompatibilitywithsystemsalreadyusingtheasynchronousdatatransferfromotherChipconproducts,asynchronoustransferisalsoincludedinCC2500.Whenasynchronoustransferisenabled,severalofthesupportmechanismsfortheMCUthatareincludedinCC2500willbedisabled,suchaspackethandlinghardware,bufferingintheFIFOandsoon.Theasynchronoustransfermodedoesnotallowtheuseofthedatawhitener,interleaver,andFEC,anditisnotpossibletouseManchesterencoding.NotethatMSKisasynchronoustransfer.

not

supported

for3

SettingPKTCTRL0.PKT_FORMATto1enablessynchronousserialmode.Inthesynchronousserialmode,dataistransferredonatwowireserialinterface.TheCC2500providesaclockthatisusedtosetupnewdataonthedatainputlineorsampledataonthedataoutputline.Datainput(TXdata)istheGDO0pin.ThispinwillautomaticallybeconfiguredasaninputwhenTXisactive.ThedataoutputpincanbeanyoftheGDOpins;thisissetbytheIOCFG0.GDO0_CFG,IOCFG1.GDO1_CFGandIOCFG2.GDO2_CFGfields.

Preambleandsyncwordinsertion/detectionmayormaynotbeactive,dependentonthesyncmodesetbytheMDMCFG2.SYNC_MODE.Ifpreambleandsyncwordisdisabled,allotherpackethandlerfeaturesandFECshouldalsobedisabled.TheMCUmustthenhandlepreambleandsyncwordinsertionanddetectioninsoftware.Ifpreambleandsyncwordinsertion/detectionislefton,allpackethandlingfeaturesandFECcanbeused.Oneexceptionisthattheaddressfilteringfeatureisunavailableinsynchronousserialmode.Whenusingthepackethandlingfeaturesinsynchronousserialmode,theCC2500willinsertanddetectthepreambleandsyncwordandtheMCUwillonlyprovide/getthedatapayload.ThisisequivalenttotherecommendedFIFOoperationmode.

SettingPKTCTRL0.PKT_FORMATenablesasynchronousserialmode.

InTX,theGDO0pinisusedfordatainput(TXdata).DataoutputcanbeonGDO0,GDO1orGDO2.ThisissetbytheIOCFG0.GDO0_CFG,IOCFG1.GDO1_CFGandIOCFG2.GDO2_CFGfields.

TheCC2500modulatorsamplestheleveloftheasynchronousinput8timesfasterthantheprogrammeddatarate.Thetimingrequirementfortheasynchronousstreamisthattheerrorinthebitperiodmustbelessthanoneeighthoftheprogrammeddatarate.

31SystemConsiderationsandGuidelines

31.1

SRDRegulations

aspectsoftheseregulationscanbefoundinApplicationNoteAN032[2].

Pleasenotethatcompliancewithregulationsisdependentoncompletesystemperformance.Itisthecustomer’sresponsibilitytoensurethatthesystemcomplieswithregulations.

Internationalregulationsandnationallawsregulatetheuseofradioreceiversandtransmitters.Themostimportantregulationsforthe2.4GHzbandareEN300440andEN300328(Europe),FCCCFR47part15.247and15.249(USA),andARIBSTD-T66(Japan).Asummaryofthemostimportant

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CC250031.2

FrequencyHoppingChannelSystems

and

Multi-timeisreducedfromapproximately720µstoapproximately150µs.Theblankingintervalbetweeneachfrequencyhopisthenapproximately240us

Thereisatradeoffbetweenblankingtimeandmemoryspaceneededforstoringcalibrationdatainnon-volatilememory.Solution2)abovegivestheshortestblankinginterval,butrequiresmorememoryspacetostorecalibrationvalues.Solution3)givesapproximately570µssmallerblankingintervalthansolution1).31.3

WidebandModulationnotUsingSpreadSpectrum

The2.400–2.4835GHzbandissharedbymanysystemsbothinindustrial,officeandhomeenvironments.Itisthereforerecommendedtousefrequencyhoppingspreadspectrum(FHSS)oramulti-channelprotocolbecausethefrequencydiversitymakesthesystemmorerobustwithrespecttointerferencefromothersystemsoperatinginthesamefrequencyband.FHSSalsocombatsmultipathfading.

CC2500ishighlysuitedforFHSSormulti-channelsystemsduetoitsagilefrequencysynthesizerandeffectivecommunicationinterface.Usingthepackethandlingsupportanddatabufferingisalsobeneficialinsuchsystemsasthesefeatureswillsignificantlyoffloadthehostcontroller.

Chargepumpcurrent,VCOcurrentandVCOcapacitancearraycalibrationdataisrequiredforeachfrequencywhenimplementingfrequencyhoppingforCC2500.Thereare3waysofobtainingthecalibrationdatafromthechip:

1)Frequencyhoppingwithcalibrationforeachhop.ThePLLcalibrationtimeisapproximately720µs.Theblankingintervalbetweeneachfrequencyhopisthenapproximately810us.2)FastfrequencyhoppingwithoutcalibrationforeachhopcanbedonebycalibratingeachfrequencyatstartupandsavingtheresultingFSCAL3,FSCAL2andFSCAL1registervaluesinMCUmemory.Betweeneachfrequencyhop,thecalibrationprocesscanthenbereplacedbywritingtheFSCAL3,FSCAL2andFSCAL1registervaluescorrespondingtothenextRFfrequency.ThePLLturnontimeisapproximately90µs.Theblankingintervalbetweeneachfrequencyhopisthenapproximately90us.TheVCOcurrentcalibrationresultisavailableinFSCAL2andisnotdependentontheRFfrequency.NeitheristhechargepumpcurrentcalibrationresultavailableinFSCAL3.Thesamevaluecanthereforebeusedforallfrequencies.

3)Runcalibrationonasinglefrequencyatstartup.Nextwrite0toFSCAL3[5:4]todisablethechargepumpcalibration.AfterwritingtoFSCAL3[5:4]strobeSRX(orSTX)withMCSM0.FS_AUTOCAL=1foreachnewfrequencyhop.Thatis,VCOcurrentandVCOcapacitancecalibrationisdonebutnotchargepumpcurrentcalibration.Whenchargepumpcurrentcalibrationisdisabledthecalibration

SWRS040C

DigitalmodulationsystemsunderFCCpart15.247includes2-FSKandGFSKmodulation.Amaximumpeakoutputpowerof1W(+30dBm)isallowedifthe6dBbandwidthofthemodulatedsignalexceeds500kHz.Inaddition,thepeakpowerspectraldensityconductedtotheantennashallnotbegreaterthan+8dBminany3kHzband.

Operatingathighdataratesandhighfrequencyseparation,theCC2500issuitedforsystemstargetingcompliancewithdigitalmodulationsystemsasdefinedbyFCCpart15.247.Anexternalpoweramplifierisneededtoincreasetheoutputabove+1dBm.31.4

DataBurstTransmissions

ThehighmaximumdatarateofCC2500opensupforbursttransmissions.Alowaveragedataratelink(e.g.10kBaud),canberealizedusingahigherover-the-airdatarate.Bufferingthedataandtransmittinginburstsathighdatarate(e.g.500kBaud)willreducethetimeinactivemode,andhencealsoreducetheaveragecurrentconsumptionsignificantly.Reducingthetimeinactivemodewillreducethelikelihoodofcollisionswithothersystems,e.g.WLAN.31.5

ContinuousTransmissions

IndatastreamingapplicationstheCC2500opensupforcontinuoustransmissionsat500kBaudeffectivedatarate.AsthemodulationisdonewithaclosedloopPLL,thereisnolimitationinthelengthofatransmission.(Openloopmodulationusedinsometransceiversoftenpreventsthiskindofcontinuousdatastreamingandreducestheeffectivedatarate.)

Page55of

CC250031.6

CrystalDriftCompensation

TheCC2500hasaveryfinefrequencyresolution(seeTable9).Thisfeaturecanbeusedtocompensateforfrequencyoffsetanddrift.

Thefrequencyoffsetbetweenan‘external’transmitterandthereceiverismeasuredintheCC2500andcanbereadbackfromtheFREQESTstatusregisterasdescribedinSection14.1.Themeasuredfrequencyoffsetcanbeusedtocalibratethefrequencyusingthe‘external’transmitterasthereference.Thatis,thereceivedsignalofthedevicewillmatchthereceiver’schannelfilterbetter.Inthesamewaythecentrefrequencyofthetransmittedsignalwillmatchthe‘external’transmitter’ssignal.31.7

SpectrumEfficientModulation

3.TheCC25XXFoldedDipolereferencedesign[8]containsschematicsandlayoutfilesforaCC2500EMwithafoldeddipolePCBantenna.PleaseseeDN004[9]formoredetailsonthisdesign.

AHC-49typeSMDcrystalisusedintheCC2500EMreferencedesign[4].Notethatthecrystalpackagestronglyinfluencestheprice.InasizeconstrainedPCBdesignasmaller,butmoreexpensive,crystalmaybeused.31.9

BatteryOperatedSystems

Inlowpowerapplications,theSLEEPstatewiththecrystaloscillatorcoreswitchedoffshouldbeusedwhentheCC2500isnotactive.ItispossibletoleavethecrystaloscillatorcorerunningintheSLEEPstateifstart-uptimeiscritical.

TheWORfunctionalityshouldbeusedinlowpowerapplications.31.10

IncreasingOutputPower

CC2500alsohasthepossibilitytouseGaussianshaped2-FSK(GFSK).Thisspectrum-shapingfeatureimprovesadjacentchannelpower(ACP)andoccupiedbandwidth.In‘true’2-FSKsystemswithabruptfrequencyshifting,thespectrumisinherentlybroad.Bymakingthefrequencyshift‘softer’,thespectrumcanbemadesignificantlynarrower.Thus,higherdataratescanbetransmittedinthesamebandwidthusingGFSK.

31.8

LowCostSystems

Insomeapplicationsitmaybenecessarytoextendthelinkrange.Addinganexternalpoweramplifieristhemosteffectivewayofdoingthis.

Thepoweramplifiershouldbeinsertedbetweentheantennaandthebalun,andtwoT/RswitchesareneededtodisconnectthePAinRXmode.SeeFigure29.

Adifferentialantennawilleliminatetheneedforabalun,andtheDCbiasingcanbeachievedintheantennatopology,seeFigure

Antenna

FilterPABalunCC2500T/RswitchT/Rswitch

Figure29.BlockDiagramofCC2500UsagewithExternalPowerAmplifier

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CC250032ConfigurationRegisters

TheconfigurationofCC2500isdonebyprogramming8-bitregisters.TheoptimumconfigurationdatabasedonselectedsystemparametersaremosteasilyfoundbyusingtheSmartRFStudiosoftware[5].Completedescriptionsoftheregistersaregiveninthefollowingtables.Afterchipreset,alltheregistershavedefaultvaluesasshowninthetables.Theoptimumregistersettingmightdifferfromthedefaultvalue.AfteraresetallregistersthatshallbedifferentfromthedefaultvaluethereforeneedstobeprogrammedthroughtheSPIinterface.

Thereare13commandstroberegisters,listedinTable34.Accessingtheseregisterswillinitiatethechangeofaninternalstateormode.Thereare47normal8-bitconfigurationregisters,listedinTable35.Manyoftheseregistersarefortestpurposesonly,andneednotbewrittenfornormaloperationofCC2500.

Address0x300x310x320x330x340x350x360x380x390x3A0x3B0x3C0x3D

StrobeNameSRESSFSTXONSXOFFSCALSRXSTXSIDLESWORSPWDSFRXSFTXSWORRSTSNOP

DescriptionResetchip.

Enableandcalibratefrequencysynthesizer(ifMCSM0.FS_AUTOCAL=1).IfinRX(withCCA):Gotoawaitstatewhereonlythesynthesizerisrunning(forquickRX/TXturnaround).Turnoffcrystaloscillator.

Calibratefrequencysynthesizerandturnitoff.SCALcanbestrobedfromIDLEmodewithoutsettingmanualcalibrationmode(MCSM0.FS_AUTOCAL=0)

EnableRX.PerformcalibrationfirstifcomingfromIDLEandMCSM0.FS_AUTOCAL=1.InIDLEstate:EnableTX.PerformcalibrationfirstifMCSM0.FS_AUTOCAL=1.IfinRXstateandCCAisenabled:OnlygotoTXifchannelisclear.

ExitRX/TX,turnofffrequencysynthesizerandexitWake-On-Radiomodeifapplicable.StartautomaticRXpollingsequence(Wake-on-Radio)asdescribedinSection19.5ifWORCTRL.RC_PD=0.

EnterpowerdownmodewhenCSngoeshigh.

FlushtheRXFIFObuffer.OnlyissueSFRXinIDLEorRXFIFO_OVERFLOWstates.FlushtheTXFIFObuffer.OnlyissueSFTXinIDLEorTXFIFO_UNDERFLOWstates.ResetrealtimeclocktoEvent1value.

Nooperation.Maybeusedtogetaccesstothechipstatusbyte.

Therearealso12statusregisters,whicharelistedinTable36.Theseregisters,whichareread-only,containinformationaboutthestatusofCC2500.

ThetwoFIFOsareaccessedthroughone8-bitregister.WriteoperationswritetotheTXFIFO,whilereadoperationsreadfromtheRXFIFO.DuringtheheaderbytetransferandwhilewritingdatatoaregisterortheTXFIFO,astatusbyteisreturnedontheSOline.ThisstatusbyteisdescribedinTable17onpage23.

Table37summarizestheSPIaddressspace.TheaddresstouseisgivenbyaddingthebaseaddresstotheleftandtheburstandR/Wbitsonthetop.Notethattheburstbithasdifferentmeaningforbaseaddressesaboveandbelow0x2F.

Table34:CommandStrobes

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CC2500Address0x000x010x020x030x040x050x060x070x080x090x0A0x0B0x0C0x0D0x0E0x0F0x100x110x120x130x140x150x160x170x180x190x1A0x1B0x1C0x1D0x1E0x1F0x200x210x220x230x240x250x260x270x280x290x2A0x2B0x2C0x2D0x2E

RegisterIOCFG2IOCFG1IOCFG0FIFOTHRSYNC1SYNC0PKTLENPKTCTRL1PKTCTRL0ADDRCHANNRFSCTRL1FSCTRL0FREQ2FREQ1FREQ0MDMCFG4MDMCFG3MDMCFG2MDMCFG1MDMCFG0DEVIATNMCSM2MCSM1MCSM0FOCCFGBSCFGAGCTRL2AGCTRL1AGCTRL0WOREVT1WOREVT0WORCTRLFREND1FREND0FSCAL3FSCAL2FSCAL1FSCAL0RCCTRL1RCCTRL0FSTESTPTESTAGCTESTTEST2TEST1TEST0

Description

GDO2outputpinconfigurationGDO1outputpinconfigurationGDO0outputpinconfigurationRXFIFOandTXFIFOthresholdsSyncword,highbyteSyncword,lowbytePacketlength

PacketautomationcontrolPacketautomationcontrolDeviceaddressChannelnumber

FrequencysynthesizercontrolFrequencysynthesizercontrolFrequencycontrolword,highbyteFrequencycontrolword,middlebyteFrequencycontrolword,lowbyteModemconfigurationModemconfigurationModemconfigurationModemconfigurationModemconfigurationModemdeviationsetting

MainRadioControlStateMachineconfigurationMainRadioControlStateMachineconfigurationMainRadioControlStateMachineconfigurationFrequencyOffsetCompensationconfigurationBitSynchronizationconfigurationAGCcontrolAGCcontrolAGCcontrol

HighbyteEvent0timeoutLowbyteEvent0timeoutWakeOnRadiocontrolFrontendRXconfigurationFrontendTXconfigurationFrequencysynthesizercalibrationFrequencysynthesizercalibrationFrequencysynthesizercalibrationFrequencysynthesizercalibrationRCoscillatorconfigurationRCoscillatorconfiguration

FrequencysynthesizercalibrationcontrolProductiontestAGCtest

VarioustestsettingsVarioustestsettingsVarioustestsettings

PreservedinSLEEPState

YesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesYesNoNoNoNoNoNo

DetailsonPageNumber

6161616262626263656565656566666768686970717273747576777778787879797980808080808081818181

Table35:ConfigurationRegistersOverview

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CC2500Address0x30(0xF0)0x31(0xF1)0x32(0xF2)0x33(0xF3)0x34(0xF4)0x35(0xF5)0x36(0xF6)0x37(0xF7)0x38(0xF8)0x39(0xF9)0x3A(0xFA)0x3B(0xFB)0x3C(0xFC)0x3D(0xFD)

RegisterPARTNUMVERSIONFREQEST

LQIRSSIMARCSTATEWORTIME1WORTIME0PKTSTATUSVCO_VC_DACTXBYTESRXBYTESRCCTRL1_STATUSRCCTRL0_STATUS

Description

DetailsonPageNumber

8181818282828383838383848484

CC2500partnumberCurrentversionnumberFrequencyoffsetestimate

DemodulatorestimateforLinkQualityReceivedsignalstrengthindicationControlstatemachinestateHighbyteofWORtimerLowbyteofWORtimer

CurrentGDOxstatusandpacketstatusCurrentsettingfromPLLcalibrationmoduleUnderflowandnumberofbytesintheTXFIFOOverflowandnumberofbytesintheRXFIFOLastRCoscillatorcalibrationresultLastRCoscillatorcalibrationresult

Table36:StatusRegistersOverview

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CC2500Write

Read

SinglebyteBurstSinglebyteBurst+0x00

+0x40

+0x80

+0xC0

0x00IOCFG20x01IOCFG10x02IOCFG00x03FIFOTHR0x04SYNC10x05SYNC00x06PKTLEN0x07PKTCTRL10x08PKTCTRL00x09ADDR0x0ACHANNR0x0BFSCTRL10x0CFSCTRL00x0DFREQ20x0EFREQ10x0FFREQ00x10MDMCFG4le0x11MDMCFG3ibs0x12MDMCFG2sop0x13MDMCFG1ss0x14MDMCFG0cec0x15DEVIATNatsr0x16MCSM2bu0x17MCSM1,sr0x18MCSM0tesi0x19FOCCFGger0x1ABSCFGniot0x1BAGCCTRL2aru0x1CAGCCTRL1igfn0x1DAGCCTRL0oc0x1EWOREVT1W/0x1FWOREVT0R0x20WORCTRL0x21FREND10x22FREND00x23FSCAL30x24FSCAL20x25FSCAL10x26FSCAL00x27RCCTRL10x28RCCTRL00x29FSTEST0x2APTEST0x2BAGCTEST0x2CTEST20x2DTEST10x2ETEST0

0x2F0x30SRESSRESPARTNUM0x31SFSTXONSFSTXONVERSION)yl0x32SXOFFSXOFFFREQEST

on0x33SCALSCALLQIda0x34SRXSRXRSSIer(0x35STXSTXMARCSTATEsret0x36SIDLESIDLEWORTIME1sig0x37WORTIME0ers0x38SWORSWORPKTSTATUSutasrt0x39SPWDSPWDVCO_VC_DACset,ssi0x3ASFRXSFRXTXBYTESbeegr0x3BSFTXSFTXRXBYTES

orettsy0x3CSWORRSTSWORRSTRCCTRL1_STATUSdbnitl0x3DSNOPSNOPRCCTRL0_STATUS

amum0x3EPATABLEPATABLEPATABLEPATABLEmdn0x3F

TXFIFO

RXFIFO

RXFIFOCoaTable37:SPIAddressSpace

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CC250032.1

ConfigurationRegisterDetails–RegisterswithPreservedValuesinSLEEPState

0x00:IOCFG2–GDO2OutputPinConfiguration

Bit765:0

FieldNameReservedGDO2_INVGDO2_CFG[5:0]

041(0x29)Reset

R/WR0R/WR/W

Invertoutput,i.e.selectactivelow(1)/high(0)DefaultisCHIP_RDYn(seeTable33onpage53).Description

0x01:IOCFG1–GDO1OutputPinConfiguration

Bit765:0

FieldNameGDO_DSGDO1_INVGDO1_CFG[5:0]

Reset0046(0x2E)

R/WR/WR/WR/W

Description

Sethigh(1)orlow(0)outputdrivestrengthontheGDOpins.

Invertoutput,i.e.selectactivelow(1)/high(0)Defaultis3-state(seeTable33onpage53)

0x02:IOCFG0–GDO0OutputPinConfiguration

Bit765:0

FieldName

TEMP_SENSOR_ENABLEGDO0_INVGDO0_CFG[5:0]

Reset0063(0x3F)

R/WR/WR/WR/W

Description

Enableanalogtemperaturesensor.Write0inallotherregisterbitswhenusingtemperaturesensor.Invertoutput,i.e.selectactivelow(1)/high(0)DefaultisCLK_XOSC/192(seeTable33onpage53).

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CC25000x03:FIFOTHR–RXFIFOandTXFIFOThresholds

Bit7:43:0

FieldNameReservedFIFO_THR[3:0]

Reset07(0111)

R/WR0R/W

Description

Write0forcompatibilitywithpossiblefutureextensionsSetthethresholdfortheTXFIFOandRXFIFO.ThethresholdisexceededwhenthenumberofbytesintheFIFOisequaltoorhigherthanthethresholdvalue.Setting0(0000)1(0001)2(0010)3(0011)4(0100)5(0101)6(0110)7(0111)8(1000)9(1001)10(1010)11(1011)12(1100)13(1101)14(1110)15(1111)

BytesinTXFIFO

615753494137332925211713951

BytesinRXFIFO

48121620242832304448525660

0x04:SYNC1–SyncWord,HighByte

Bit7:0

FieldNameSYNC[15:8]

Reset211(0xD3)

R/WR/W

Description

8MSBof16-bitsyncword

0x05:SYNC0–SyncWord,LowByte

Bit7:0

FieldNameSYNC[7:0]

Reset145(0x91)

R/WR/W

Description

8LSBof16-bitsyncword

0x06:PKTLEN–PacketLength

Bit7:0

FieldNamePACKET_LENGTH

Reset255(0xFF)

R/WR/W

Description

Indicatesthepacketlengthwhenfixedpacketlengthisenabled.Ifvariablelengthpacketsareused,thisvalueindicatesthemaximumlengthpacketsallowed.

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CC25000x07:PKTCTRL1–PacketAutomationControl

Bit7:5

FieldNamePQT[2:0]

Reset0(000)

R/WR/W

Description

Preamblequalityestimatorthreshold.Thepreamblequality

estimatorincreasesaninternalcounterbyoneeachtimeabitisreceivedthatisdifferentfromthepreviousbit,anddecreasesthecounterby8eachtimeabitisreceivedthatisthesameasthelastbit.

Athresholdof4∙PQTforthiscounterisusedtogatesyncworddetection.WhenPQT=0asyncwordisalwaysaccepted.

Reserved

CRC_AUTOFLUSH

R0R/W

EnableautomaticflushofRXFIFOwhenCRCisnotOK.ThisrequiresthatonlyonepacketisintheRXFIFOandthatpacketlengthislimitedtotheRXFIFOsize.

PKTCTRL0.CC2400_ENmustbe0(default)fortheCRCautoflushfunctiontoworkcorrectly.

APPEND_STATUS

R/W

Whenenabled,twostatusbyteswillbeappendedtothepayloadofthepacket.ThestatusbytescontainRSSIandLQIvalues,aswellastheCRCOKflag.

Controlsaddresscheckconfigurationofreceivedpackages.Setting0(00)1(01)2(10)3(11)

AddresscheckconfigurationNoaddresscheck

Addresscheck,nobroadcast

Addresscheckand0(0x00)broadcastAddresscheckand0(0x00)and255(0xFF)broadcast

1:0ADR_CHK[1:0]0(00)R/W

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CC25000x08:PKTCTRL0–PacketAutomationControl

Bit76

FieldNameReservedWHITE_DATA

1Reset

R/WR0R/W

Turndatawhiteningon/off0:Whiteningoff1:Whiteningon

DatawhiteningcanonlybeusedwhenPKTCTRL0.CC2400_EN=0(default).

5:4

PKT_FORMAT[1:0]

0(00)

R/W

FormatofRXandTXdataSetting0(00)1(01)

Packetformat

Normalmode,useFIFOsforRXandTXSynchronousserialmode,usedforbackwardscompatibility.DatainonGDO0

RandomTXmode;sendsrandomdatausingPN9generator.Usedfortest.

Worksasnormalmode,setting0(00),inRX.Asynchronousserialmode.DatainonGDO0anddataoutoneitheroftheGDO0pins

Description

2(10)

3(11)

CC2400_EN

R/W

EnableCC2400support.UsesameCRCimplementationasCC2400.

PKTCTRL1.CRC_AUTOFLUSHmustbe0ifPKTCTRL0.CC2400_EN=1.

PKTCTRL0.WHITE_DATAmustbe0ifPKTCTRL0.CC2400_EN=1.

2CRC_EN1R/W1:CRCcalculationinTXandCRCcheckinRXenabled0:CRCdisabledforTXandRX

1:0LENGTH_CONFIG[1:0]1(01)R/WConfigurethepacketlengthSetting0(00)1(01)2(10)3(11)

Packetlengthconfiguration

Fixedpacketlengthmode.LengthconfiguredinPKTLENregister

Variablepacketlengthmode.PacketlengthconfiguredbythefirstbyteaftersyncwordInfinitepacketlengthmodeReserved

0x09:ADDR–DeviceAddress

Bit7:0

FieldNameDEVICE_ADDR[7:0]

Reset0(0x00)

R/WR/W

Description

Addressusedforpacketfiltration.Optionalbroadcastaddressesare0(0x00)and255(0xFF).

0x0A:CHANNR–ChannelNumber

Bit7:0

FieldNameCHAN[7:0]

Reset0(0x00)

R/WR/W

Description

The8-bitunsignedchannelnumber,whichismultipliedbythechannelspacingsettingandaddedtothebasefrequency.

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CC25000x0B:FSCTRL1–FrequencySynthesizerControl

Bit7::0FieldNameReservedFREQ_IF[4:0]15(0x0F)ResetR/WR0R/WThedesiredIFfrequencytoemployinRX.SubtractedfromFSbasefrequencyinRXandcontrolsthedigitalcomplexmixerinthedemodulator.DescriptionfIFfXOSCFREQ_IF210ThedefaultvaluegivesanIFfrequencyof381kHz,assuminga26.0MHzcrystal.0x0C:FSCTRL0–FrequencySynthesizerControl

Bit7:0

FieldNameFREQOFF[7:0]

Reset0(0x00)

R/WR/W

Description

FrequencyoffsetaddedtothebasefrequencybeforebeingusedbytheFS.(2’scomplement).

ResolutionisFXTAL/214(1.59-1.65kHz);rangeis±202kHzto±210kHz,dependentofXTALfrequency.

0x0D:FREQ2–FrequencyControlWord,HighByte

Bit7:65:0FieldNameFREQ[23:22]FREQ[21:16]Reset1(01)30(0x1E)R/WRR/WDescriptionFREQ[23:22]isalwaysbinary01(theFREQ2registerisintherange85to95with26-27MHzcrystal)FREQ[23:0]isthebasefrequencyforthefrequencysynthesiserinincrementsofFXOSC/216.fcarrierfXOSCFREQ23:02160x0E:FREQ1–FrequencyControlWord,MiddleByte

Bit7:0

FieldNameFREQ[15:8]

Reset196(0xC4)

R/WR/W

DescriptionRef.FREQ2register

0x0F:FREQ0–FrequencyControlWord,LowByte

Bit7:0

FieldNameFREQ[7:0]

Reset236(0xEC)

R/WR/W

DescriptionRef.FREQ2register

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CC25000x10:MDMCFG4–ModemConfiguration

Bit7:65:4FieldNameCHANBW_E[1:0]CHANBW_M[1:0]Reset2(10)0(00)R/WR/WR/WSetsthedecimationratioforthedelta-sigmaADCinputstreamandthusthechannelbandwidth.DescriptionBWchannelfXOSC8(4CHANBW_M)·2CHANBW_EThedefaultvaluesgive203kHzchannelfilterbandwidth,assuminga26.0MHzcrystal.3:0DRATE_E[3:0]12(1100)R/WTheexponentoftheuserspecifiedsymbolrate0x11:MDMCFG3–ModemConfiguration

Bit7:0FieldNameDRATE_M[7:0]Reset34(0x22)R/WR/WDescriptionThemantissaoftheuserspecifiedsymbolrate.Thesymbolrateisconfiguredusinganunsigned,floating-pointnumberwith9-bitmantissaand4-bitexponent.The9thbitisahidden‘1’.Theresultingdatarateis:RDATA256DRATE_M2DRATE_Ef228XOSCThedefaultvaluesgiveadatarateof115.051kBaud(closestsettingto115.2kBaud),assuminga26.0MHzcrystal.SWRS040CPage66of

CC25000x12:MDMCFG2–ModemConfiguration

Bit7

FieldNameDEM_DCFILT_OFF

Reset0

R/WR/W

Description

DisabledigitalDCblockingfilterbeforedemodulator.0=Enable(bettersensitivity)

1=Disable(currentoptimized).Onlyfordatarates≤250kBaud

TherecommendedIFfrequencychangeswhentheDCblockingisdisabled.PleaseuseSmartRFStudio[5]tocalculatecorrectregistersetting.

6:4

MOD_FORMAT[2:0]

0(000)

R/W

ThemodulationformatoftheradiosignalSetting0(000)1(001)2(010)3(011)4(100)5(101)6(110)7(111)

MANCHESTER_EN

R/W

Modulationformat2-FSKGFSK-OOK---MSK

EnablesManchesterencoding/decoding.0=Disable1=Enable

2:0SYNC_MODE[2:0]2(010)R/WCombinedsync-wordqualifiermode.

Thevalues0(000)and4(100)disablespreambleandsyncwordtransmissioninTXandpreambleandsyncworddetectioninRX.

Thevalues1(001),2(010),5(101)and6(110)

enables16-bitsyncwordtransmissioninTXand16-bitssyncworddetectioninRX.Only15of16bitsneedtomatchinRXwhenusingsetting1(001)or5(101).Thevalues3(011)and7(111)enablesrepeatedsyncwordtransmissioninTXand32-bitssyncworddetectioninRX(only30of32bitsneedtomatch).Setting0(000)1(001)2(010)3(011)4(100)5(101)6(110)7(111)

Sync-wordqualifiermodeNopreamble/sync

15/16syncwordbitsdetected16/16syncwordbitsdetected30/32syncwordbitsdetectedNopreamble/sync,carrier-senseabovethreshold

15/16+carrier-senseabovethreshold16/16+carrier-senseabovethreshold30/32+carrier-senseabovethreshold

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CC25000x13:MDMCFG1–ModemConfiguration

Bit7

FieldNameFEC_EN

Reset0

R/WR/W

Description

EnableForwardErrorCorrection(FEC)withinterleavingforpacketpayload0=Disable

1=Enable(Onlysupportedforfixedpacketlengthmode,i.e.PKTCTRL0.LENGTH_CONFIG=0)

6:4

NUM_PREAMBLE[2:0]

2(010)

R/W

SetstheminimumnumberofpreamblebytestobetransmittedSetting0(000)1(001)2(010)3(011)4(100)5(101)6(110)7(111)

3:21:0

ReservedCHANSPC_E[1:0]

2(10)

R0R/W

2bitexponentofchannelspacing

Numberofpreamblebytes23468121624

0x14:MDMCFG0–ModemConfiguration

Bit7:0FieldNameCHANSPC_M[7:0]Reset248(0xF8)R/WR/WDescription8-bitmantissaofchannelspacing.ThechannelspacingismultipliedbythechannelnumberCHANandaddedtothebasefrequency.Itisunsignedandhastheformat:fCHANNELfXOSC256CHANSPC_M2CHANSPC_E182Thedefaultvaluesgive199.951kHzchannelspacing(theclosestsettingto200kHz),assuming26.0MHzcrystalfrequency.SWRS040CPage68of

CC25000x15:DEVIATN–ModemDeviationSetting

Bit76:432:0FieldNameReservedDEVIATION_E[2:0]ReservedDEVIATION_M[2:0]7(111)4(100)ResetR/WR0R/WR0R/WWhenMSKmodulationisenabled:Setsfractionofsymbolperiodusedforphasechange.RefertotheSmartRFStudiosoftware[5]forcorrectDEVIATNsettingwhenusingMSK.When2-FSK/GFSKmodulationisenabled:Deviationmantissa,interpretedasa4-bitvaluewithMSBimplicit1.Theresultingdeviationisgivenby:DeviationexponentDescriptionfdevfxosc(8DEVIATION_M)2DEVIATION_E172Thedefaultvaluesgive±47.607kHzdeviation,assuming26.0MHzcrystalfrequency.SWRS040CPage69of

CC25000x16:MCSM2–MainRadioControlStateMachineConfiguration

Bit7:3

FieldNameReservedRX_TIME_RSSIRX_TIME_QUAL

00Reset

R/WR0R/WR/W

DescriptionReserved

DirectRXterminationbasedonRSSImeasurement(carriersense).

WhentheRX_TIMEtimerexpiresthechipstaysinRXmodeifsyncwordisfoundwhenRX_TIME_QUAL=0,oreithersyncwordisfoundorPQTissetwhenRX_TIME_QUAL=1.TimeoutforsyncwordsearchinRXforbothWORmodeandnormalRXoperation.ThetimeoutisrelativetotheprogrammedEVENT0timeout.

2:0RX_TIME[2:0]7(111)R/W

TheRXtimeoutinµsisgivenbyEVENT0·C(RX_TIME,WOR_RES)·26/X,whereCisgivenbythetablebelowandXisthecrystaloscillatorfrequencyinMHz:RX_TIME[2:0]0(000)1(001)2(010)3(011)4(100)5(101)6(110)7(111)

WOR_RES=03.60581.80290.90140.45070.220.11270.0563

Untilendofpacket

WOR_RES=118.028.01444.50722.25361.12680.56340.2817

WOR_RES=232.451916.22608.11304.05652.02821.01410.5071

WOR_RES=346.875023.437511.71885.85942.92971.480.7324

Asanexample,EVENT0=34666,WOR_RES=0andRX_TIME=6correspondsto1.95msRXtimeout,1spollingintervaland0.195%dutycycle.NotethatWOR_RESshouldbe0or1whenusingWORbecauseusing

WOR_RES>1willgiveaverylowdutycycle.InapplicationswhereWORisnotusedallsettingsofWOR_REScanbeused.

ThedutycycleusingWORisapproximatedby:RX_TIME[2:0]0(000)1(001)2(010)3(011)4(100)5(101)6(110)7(111)

WOR_RES=012.50%6.250%3.125%1.563%0.781%0.391%0.195%NA

WOR_RES=11.95%9765ppm4883ppm2441ppmNANANA

NotethattheRCoscillatormustbeenabledinordertousesetting0-6,becausethetimeoutcountsRCoscillatorperiods.WORmodedoesnotneedtobeenabled.

Thetimeoutcounterresolutionislimited:WithRX_TIME=0,thetimeoutcountisgivenbythe13MSBsofEVENT0,decreasingtothe7MSBsofEVENT0withRX_TIME=6.

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CC25000x17:MCSM1–MainRadioControlStateMachineConfiguration

Bit7:65:4

FieldNameReservedCCA_MODE[1:0]

3(11)Reset

R/WR0R/W

SelectsCCA_MODE;ReflectedinCCAsignalSetting0(00)1(01)2(10)3(11)

3:2

RXOFF_MODE[1:0]

0(00)

R/W

ClearchannelindicationAlways

IfRSSIbelowthreshold

UnlesscurrentlyreceivingapacketIfRSSIbelowthresholdunlesscurrentlyreceivingapacket

Description

SelectwhatshouldhappenwhenapackethasbeenreceivedSetting0(00)1(01)2(10)3(11)

NextstateafterfinishingpacketreceptionIDLEFSTXONTXStayinRX

ItisnotpossibletosetRXOFF_MODEtobeTXorFSTXONandatthesametimeuseCCA.

1:0

TXOFF_MODE[1:0]

0(00)

R/W

Selectwhatshouldhappenwhenapackethasbeensent(TX)Setting0(00)1(01)2(10)3(11)

NextstateafterfinishingpackettransmissionIDLEFSTXON

StayinTX(startsendingpreamble)RX

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CC25000x18:MCSM0–MainRadioControlStateMachineConfiguration

Bit7:65:4

FieldNameReserved

FS_AUTOCAL[1:0]

0(00)Reset

R/WR0R/W

AutomaticallycalibratewhengoingtoRXorTX,orbacktoIDLESetting0(00)1(01)2(10)3(11)

WhentoperformautomaticcalibrationNever(manuallycalibrateusingSCALstrobe)WhengoingfromIDLEtoRXorTX(orFSTXON)WhengoingfromRXorTXbacktoIDLEautomatically

Every4thtimewhengoingfromRXorTXtoIDLEautomatically

Description

Insomeautomaticwake-on-radio(WOR)applications,usingsetting3(11)cansignificantlyreducecurrentconsumption.

3:2

PO_TIMEOUT

1(01)

R/W

Programsthenumberoftimesthesix-bitripplecountermustexpireafterXOSChasstabilizedbeforeCHP_RDYngoeslow.IfXOSCison(stable)duringpower-down,PO_TIMEOUTshouldbesetsothattheregulateddigitalsupplyvoltagehastimetostabilizebeforeCHP_RDYngoeslow(PO_TIMEOUT=2recommended).Typicalstart-uptimeforthevoltageregulatoris50us.

IfXOSCisoffduringpower-downandtheregulateddigitalsupplyvoltagehassufficienttimetostabilizewhilewaitingforthecrystaltobestable,PO_TIMEOUTcanbesetto0.ForrobustoperationitisrecommendedtousePO_TIMEOUT=2.Setting0(00)1(01)2(10)3(11)

Expirecount116256

TimeoutafterXOSCstartApprox.2.3–2.4μsApprox.37–39μsApprox.149–155μsApprox.597–620μs

Exacttimeoutdependsoncrystalfrequency.

PIN_CTRL_ENXOSC_FORCE_ON

R/WR/W

Enablesthepinradiocontroloption

ForcetheXOSCtostayonintheSLEEPstate.

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CC25000x19:FOCCFG–FrequencyOffsetCompensationConfiguration

Bit7:65

FieldNameReserved

FOC_BS_CS_GATE

1Reset

R/WR0R/W

Ifset,thedemodulatorfreezesthefrequencyoffset

compensationandclockrecoveryfeedbackloopsuntiltheCARRIER_SENSEsignalgoeshigh.

Thefrequencycompensationloopgaintobeusedbeforeasyncwordisdetected.Setting0(00)1(01)2(10)3(11)

FOC_POST_K

R/W

Freq.compensationloopgainbeforesyncwordK2K3K4K

Description

4:3FOC_PRE_K[1:0]2(10)R/W

Thefrequencycompensationloopgaintobeusedafterasyncwordisdetected.Setting01

Freq.compensationloopgainaftersyncwordSameasFOC_PRE_KK/2

1:0FOC_LIMIT[1:0]2(10)R/W

Thesaturationpointforthefrequencyoffsetcompensationalgorithm:Setting0(00)1(01)2(10)3(11)

Saturationpoint(maxcompensatedoffset)±0(nofrequencyoffsetcompensation)±BWCHAN/8±BWCHAN/4±BWCHAN/2

FrequencyoffsetcompensationisnotsupportedforOOK;AlwaysuseFOC_LIMIT=0withthismodulationformat.

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CC25000x1A:BSCFG–BitSynchronizationConfiguration

Bit7:6

FieldNameBS_PRE_KI[1:0]

Reset1(01)

R/WR/W

Description

Theclockrecoveryfeedbackloopintegralgaintobeusedbeforeasyncwordisdetected(usedtocorrectoffsetsindatarate):Setting0(00)1(01)2(10)3(11)

5:4

BS_PRE_KP[1:0]

2(10)

R/W

ClockrecoveryloopintegralgainbeforesyncwordKI2KI3KI4KI

Theclockrecoveryfeedbackloopproportionalgaintobeusedbeforeasyncwordisdetected.Setting0(00)1(01)2(10)3(11)

ClockrecoveryloopproportionalgainbeforesyncwordKP2KP3KP4KP

3BS_POST_KI1R/W

Theclockrecoveryfeedbackloopintegralgaintobeusedafterasyncwordisdetected.Setting01

ClockrecoveryloopintegralgainaftersyncwordSameasBS_PRE_KIKI/2

2BS_POST_KP1R/W

Theclockrecoveryfeedbackloopproportionalgaintobeusedafterasyncwordisdetected.Setting01

ClockrecoveryloopproportionalgainaftersyncwordSameasBS_PRE_KPKP

1:0BS_LIMIT[1:0]0(00)R/WThesaturationpointforthedatarateoffsetcompensationalgorithm:Setting0(00)1(01)2(10)3(11)

Datarateoffsetsaturation(maxdataratedifference)±0(Nodatarateoffsetcompensationperformed)±3.125%datarateoffset±6.25%datarateoffset±12.5%datarateoffset

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CC25000x1B:AGCCTRL2–AGCControl

Bit7:6

FieldName

MAX_DVGA_GAIN[1:0]

Reset0(00)

R/WR/W

Description

ReducesthemaximumallowableDVGAgain.Setting0(00)1(01)2(10)3(11)

5:3

MAX_LNA_GAIN[2:0]

0(000)

R/W

AllowableDVGAsettingsAllgainsettingscanbeused

ThehighestgainsettingcannotbeusedThe2highestgainsettingscannotbeusedThe3highestgainsettingscannotbeused

SetsthemaximumallowableLNA+LNA2gainrelativetothemaximumpossiblegain.Setting0(000)1(001)2(010)3(011)4(100)5(101)6(110)7(111)

MaximumallowableLNA+LNA2gainMaximumpossibleLNA+LNA2gainApprox.2.6dBbelowmaximumpossiblegainApprox.6.1dBbelowmaximumpossiblegainApprox.7.4dBbelowmaximumpossiblegainApprox.9.2dBbelowmaximumpossiblegainApprox.11.5dBbelowmaximumpossiblegainApprox.14.6dBbelowmaximumpossiblegainApprox.17.1dBbelowmaximumpossiblegain

2:0MAGN_TARGET[2:0]3(011)R/W

Thesebitssetthetargetvaluefortheaveragedamplitudefromthedigitalchannelfilter(1LSB=0dB).Setting0(000)1(001)2(010)3(011)4(100)5(101)6(110)7(111)

Targetamplitudefromchannelfilter24dB27dB30dB33dB36dB38dB40dB42dB

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CC25000x1C:AGCCTRL1–AGCControl

Bit76

FieldNameReserved

AGC_LNA_PRIORITY

1Reset

R/WR0R/W

SelectsbetweentwodifferentstrategiesforLNAandLNA2gainadjustment.When1,theLNAgainisdecreasedfirst.When0,theLNA2gainisdecreasedtominimumbeforedecreasingLNAgain.

Setstherelativechangethresholdforassertingcarriersense.Setting0(00)1(01)2(10)3(11)

3:0

CARRIER_SENSE_ABS_THR[3:0]

(0000)

R/W

Carriersenserelativethreshold

Relativecarriersensethresholddisabled6dBincreaseinRSSIvalue10dBincreaseinRSSIvalue14dBincreaseinRSSIvalue

Description

5:4CARRIER_SENSE_REL_THR[1:0]0(00)R/W

SetstheabsoluteRSSIthresholdforassertingcarrier

sense.The2’scomplementsignedthresholdisprogrammedinstepsof1dBandisrelativetotheMAGN_TARGETsetting.Setting

Carriersenseabsolutethreshold

(EqualtochannelfilteramplitudewhenAGChasnotdecreasedgain)

-8(1000)-7(1001)…-1(1111)0(0000)1(0001)…7(0111)

Absolutecarriersensethresholddisabled7dBbelowMAGN_TARGETsetting…

1dBbelowMAGN_TARGETsettingAtMAGN_TARGETsetting

1dBaboveMAGN_TARGETsetting…

7dBaboveMAGN_TARGETsetting

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CC25000x1D:AGCCTRL0–AGCControl

Bit7:6

FieldNameHYST_LEVEL[1:0]

Reset2(10)

R/WR/W

Description

Setsthelevelofhysteresisonthemagnitudedeviation(internalAGCsignalthatdeterminesgainchanges).Setting0(00)1(01)2(10)3(11)

5:4

WAIT_TIME[1:0]

1(01)

R/W

Description

Nohysteresis,smallsymmetricdeadzone,highgain

Lowhysteresis,smallasymmetricdeadzone,mediumgain

Mediumhysteresis,mediumasymmetricdeadzone,mediumgain

Largehysteresis,largeasymmetricdeadzone,lowgain

SetsthenumberofchannelfiltersamplesfromagainadjustmenthasbeenmadeuntiltheAGCalgorithmstartsaccumulatingnewsamples.Setting0(00)1(01)2(10)3(11)

Channelfiltersamples8162432

3:2AGC_FREEZE[1:0]0(00)R/WControlswhentheAGCgainshouldbefrozen.Setting0(00)1(01)2(10)

Function

Normaloperation.Alwaysadjustgainwhenrequired.

Thegainsettingisfrozenwhenasyncwordhasbeenfound.

Manuallyfreezestheanaloggainsettingandcontinuetoadjustthedigitalgain.

Manuallyfreezesboththeanalogandthedigitalgainsettings.Usedformanuallyoverridingthegain.

3(11)

1:0

FILTER_LENGTH[1:0]

1(01)

R/W

Setstheaveraginglengthfortheamplitudefromthechannelfilter.SetstheOOKdecisionboundaryforOOKreception.Setting0(00)1(01)2(10)3(11)

Channelfiltersamples81632

OOKdecision4dB8dB12dB16dB

0x1E:WOREVT1–HighByteEvent0Timeout

Bit7:0FieldNameEVENT0[15:8]Reset135(0x87)R/WR/WDescriptionHighbyteofEvent0timeoutregistertEvent0750EVENT025WOR_RESfXOSCSWRS040CPage77of

CC25000x1F:WOREVT0–LowByteEvent0Timeout

Bit7:0

FieldNameEVENT0[7:0]

Reset107(0x6B)

R/WR/W

Description

LowbyteofEvent0timeoutregister.

ThedefaultEvent0valuegives1.0stimeout,assuminga26.0MHzcrystal.

0x20:WORCTRL–WakeOnRadioControl

Bit76:4

FieldNameRC_PDEVENT1[2:0]

Reset17(111)

R/WR/WR/W

Description

PowerdownsignaltoRCoscillator.Whenwrittento0,automaticinitialcalibrationwillbeperformed

Timeoutsettingfromregisterblock.DecodedtoEvent1timeout.RCoscillatorclockfrequencyequalsFXOSC/750,whichis34.7-36kHz,dependingoncrystalfrequency.ThetablebelowliststhenumberofclockperiodsafterEvent0beforeEvent1timesout.Setting0(000)1(001)2(010)3(011)4(100)5(101)6(110)7(111)

321:0

RC_CALReservedWOR_RES[1:0]

0(00)1

R/WR0R/W

ControlstheEvent0resolutionaswellasmaximumtimeoutoftheWORmoduleandmaximumtimeoutundernormalRXoperation:Setting0(00)1(01)2(10)3(11)

Resolution(1LSB)1period(28–29μs)25periods(0.–0.92ms)210periods(28–30ms)215periods(0.91–0.94s)

Maxtimeout1.8–1.9seconds58–61seconds31–32minutes16.5–17.2hours

t_event1

4(0.111–0.115ms)6(0.167–0.173ms)8(0.222–0.230ms)12(0.333–0.346ms)16(0.444–0.462ms)24(0.667–0.692ms)32(0.8–0.923ms)48(1.333–1.385ms)

Enables(1)ordisables(0)theRCoscillatorcalibration.

NotethatWOR_RESshouldbe0or1whenusingWORbecauseWOR_RES>1willgiveaverylowdutycycle.

InnormalRXoperationallsettingsofWOR_REScanbeused.

0x21:FREND1–FrontEndRXConfiguration

Bit7:65:43:21:0

FieldNameLNA_CURRENT[1:0]LNA2MIX_CURRENT[1:0]LODIV_BUF_CURRENT_RX[1:0]MIX_CURRENT[1:0]

Reset1(01)1(01)1(01)2(10)

R/WR/WR/WR/WR/W

Description

Adjustsfront-endLNAPTATcurrentoutputAdjustsfront-endPTAToutputs

AdjustscurrentinRXLObuffer(LOinputtomixer)Adjustscurrentinmixer

SWRS040CPage78of

CC25000x22:FREND0–FrontEndTXconfiguration

Bit7:65:432:0

FieldNameReserved

LODIV_BUF_CURRENT_TX[1:0]ReservedPA_POWER[2:0]

0(000)1(01)Reset

R/WR0R/WR0R/W

SelectsPApowersetting.Thisvalueisanindextothe

PATABLE.InOOKmode,thisselectsthePATABLEindextousewhentransmittinga‘1’.PATABLEindexzeroisusedinOOKwhentransmittinga‘0’.

AdjustscurrentTXLObuffer(inputtoPA).ThevaluetouseinthisfieldisgivenbytheSmartRFStudiosoftware[5].Description

0x23:FSCAL3–FrequencySynthesizerCalibration

Bit7:6

FieldNameFSCAL3[7:6]

Reset2(10)

R/WR/W

Description

Frequencysynthesizercalibrationconfiguration.ThevaluetowriteinthisregisterbeforecalibrationisgivenbytheSmartRFStudiosoftware[5].

Disablechargepumpcalibrationstagewhen0

Frequencysynthesizercalibrationresultregister.Digitalbitvectordefiningthechargepumpoutputcurrent,onanexponentialscale:IOUT=I0·2FSCAL3[3:0]/4

FastfrequencyhoppingwithoutcalibrationforeachhopcanbedonebycalibratingupfrontforeachfrequencyandsavingtheresultingFSCAL3,FSCAL2andFSCAL1registervalues.Betweeneachfrequencyhop,calibrationcanbereplacedbywritingtheFSCAL3,FSCAL2andFSCAL1registervaluescorrespondingtothenextRFfrequency.

5:43:0

CHP_CURR_CAL_EN[1:0]FSCAL3[3:0]

2(10)9

(1001)

R/WR/W

0x24:FSCAL2–FrequencySynthesizerCalibration

Bit7:6:0

FieldNameReserved

VCO_CORE_H_ENFSCAL2[4:0]

010(0x0A)Reset

R/WR0R/WR/W

Choosehigh(1)/low(0)VCO

Frequencysynthesizercalibrationresultregister.VCOcurrentcalibrationresultandoverridevalue

SWRS040CPage79of

CC25000x25:FSCAL1–FrequencySynthesizerCalibration

Bit7:65:0

FieldNameReservedFSCAL1[5:0]

32(0x20)Reset

R/WR0R/W

Frequencysynthesizercalibrationresultregister.CapacitorarraysettingforVCOcoarsetuning.

0x26:FSCAL0–FrequencySynthesizerCalibration

Bit76:0

FieldNameReservedFSCAL0[6:0]

13(0x0D)Reset

R/WR0R/W

Frequencysynthesizercalibrationcontrol.ThevaluetouseinthisregisterisgivenbytheSmartRFStudiosoftware[5].Description

0x27:RCCTRL1–RCOscillatorConfiguration

Bit76:0

FieldNameReservedRCCTRL1[6:0]

Reset065(0x41)

R/WR0R/W

RCoscillatorconfiguration.Description

0x28:RCCTRL0–RCOscillatorConfiguration

Bit76:0

FieldNameReservedRCCTRL0[6:0]

Reset00

(0x00)

R/WR0R/W

RCoscillatorconfiguration.Description

32.2ConfigurationRegisterDetails–RegistersthatLoseProgramminginSLEEPState

0x29:FSTEST–FrequencySynthesizerCalibrationControl

Bit7:0

FieldNameFSTEST[7:0]

Reset(0x59)

R/WR/W

Description

Fortestonly.Donotwritetothisregister.

0x2A:PTEST–ProductionTest

Bit7:0

FieldNamePTEST[7:0]

Reset127(0x7F)

R/WR/W

Description

Writing0xBFtothisregistermakestheon-chiptemperaturesensoravailableintheIDLEstate.Thedefault0x7FvalueshouldthenbewrittenbackbeforeleavingtheIDLEstate.Otheruseofthisregisterisfortestonly.

SWRS040CPage80of

CC25000x2B:AGCTEST–AGCTest

Bit7:0

FieldNameAGCTEST[7:0]

Reset63(0x3F)

R/WR/W

Description

Fortestonly.Donotwritetothisregister.

0x2C:TEST2–VariousTestSettings

Bit7:0

FieldNameTEST2[7:0]

Reset136(0x88)

R/WR/W

Description

Setto0x81forimprovedsensitivityatdatarates≤100kBaud.Thetemperaturerangeisthenfrom0oCto+85oC.

0x2D:TEST1–VariousTestSettings

Bit7:0

FieldNameTEST1[7:0]

Reset49(0x31)

R/WR/W

Description

Setto0x35forimprovedsensitivityatdatarates≤100kBaud.Thetemperaturerangeisthenfrom0oCto+85oC.

0x2E:TEST0–VariousTestSettings

Bit7:210

FieldNameTEST0[7:2]VCO_SEL_CAL_ENTEST0[0]

Reset2(0x02)11

R/WR/WR/WR/W

Description

ThevaluetouseinthisregisterisgivenbytheSmartRFStudiosoftware[5].

EnableVCOselectioncalibrationstagewhen1

ThevaluetouseinthisregisterisgivenbytheSmartRFStudiosoftware[5].

32.3StatusRegisterDetails

0x30(0xF0):PARTNUM–ChipID

Bit7:0

FieldNamePARTNUM[7:0]

Reset128(0x80)

R/WR

DescriptionChippartnumber

0x31(0xF1):VERSION–ChipID

Bit7:0

FieldNameVERSION[7:0]

Reset3(0x03)

R/WR

DescriptionChipversionnumber.

0x32(0xF2):FREQEST–FrequencyOffsetEstimatefromDemodulator

Bit7:0

FieldNameFREQOFF_EST

Reset

R/WR

Description

Theestimatedfrequencyoffset(2’scomplement)ofthecarrier.ResolutionisFXTAL/214(1.59-1.65kHz);rangeis±202kHzto±210kHz,dependentofXTALfrequency.

Frequencyoffsetcompensationisonlysupportedfor2-FSK;GFSKandMSKmodulation.Thisregisterwillread0whenusingOOKmodulation.

SWRS040CPage81of

CC25000x33(0xF3):LQI–DemodulatorEstimateforLinkQuality

Bit7

FieldNameCRC_OK

Reset

R/WR

Description

ThelastCRCcomparisonmatched.Clearedwhenentering/restartingRXmode.OnlyvalidifPKTCTRL0.CC2400_EN=1.

TheLinkQualityIndicatorestimateshoweasilyareceivedsignalcanbedemodulated.Calculatedoverthesymbolsfollowingthesyncword.

6:0LQI_EST[6:0]R

0x34(0xF4):RSSI–ReceivedSignalStrengthIndication

Bit7:0

FieldNameRSSI

Reset

R/WR

Description

Receivedsignalstrengthindicator

0x35(0xF5):MARCSTATE–MainRadioControlStateMachineState

Bit7::0

FieldNameReserved

MARC_STATE[4:0]

Reset

R/WR0R

MainRadioControlFSMStateValue0(0x00)1(0x01)2(0x02)3(0x03)4(0x04)5(0x05)6(0x06)7(0x07)8(0x08)9(0x09)10(0x0A)11(0x0B)12(0x0C)13(0x0D)14(0x0E)15(0x0F)16(0x10)17(0x11)18(0x12)19(0x13)20(0x14)21(0x15)22(0x16)

StatenameSLEEPIDLEXOFFVCOON_MCREGON_MCMANCALVCOONREGONSTARTCALBWBOOSTFS_LOCKIFADCONENDCALRXRX_ENDRX_RSTTXRX_SWITCHRXFIFO_OVERFLOWFSTXONTXTX_ENDRXTX_SWITCHTXFIFO_UNDERFLOW

State(Figure15,page39)SLEEPIDLEXOFFMANCALMANCALMANCALFS_WAKEUPFS_WAKEUPCALIBRATESETTLINGSETTLINGSETTLINGCALIBRATERXRXRX

TXRX_SETTLINGRXFIFO_OVERFLOWFSTXONTXTX

RXTX_SETTLINGTXFIFO_UNDERFLOW

Description

Note:itisnotpossibletoreadbacktheSLEEPorXOFFstatenumbersbecausesettingCSnlowwillmakethechipentertheIDLEmodefromtheSLEEPorXOFFstates.

SWRS040CPage82of

CC25000x36(0xF6):WORTIME1–HighByteofWORTime

Bit7:0

FieldNameTIME[15:8]

Reset

R/WR

Description

HighbyteoftimervalueinWORmodule

0x37(0xF7):WORTIME0–LowByteofWORTime

Bit7:0

FieldNameTIME[7:0]

Reset

R/WR

Description

LowbyteoftimervalueinWORmodule

0x38(0xF8):PKTSTATUS–CurrentGDOxStatusandPacketStatus

Bit7

FieldNameCRC_OK

Reset

R/WR

Description

ThelastCRCcomparisonmatched.Clearedwhenentering/restartingRXmode.OnlyvalidifPKTCTRL0.CC2400_EN=1.Carriersense

PreambleQualityreachedChannelisclearSyncwordfound

CurrentGDO2value.Note:thereadinggivesthenon-invertedvalueirrespectivewhatIOCFG2.GDO2_INVisprogrammedto.ItisnotrecommendedtocheckforPLLlockbyreadingPKTSTATUS[2]withGDO2_CFG=0x0A.

ReservedGDO0

R0R

CurrentGDO0value.Note:thereadinggivesthenon-invertedvalueirrespectivewhatIOCFG0.GDO0_INVisprogrammedto.ItisnotrecommendedtocheckforPLLlockbyreadingPKTSTATUS[0]withGDO0_CFG=0x0A.

632

PQT_REACHEDCCASFDGDO2

RRRRR

0x39(0xF9):VCO_VC_DAC–CurrentSettingfromPLLCalibrationModule

Bit7:0

FieldNameVCO_VC_DAC[7:0]

Reset

R/WR

Description

Statusregisterfortestonly

0x3A(0xFA):TXBYTES–UnderflowandNumberofBytes

Bit76:0

FieldName

TXFIFO_UNDERFLOWNUM_TXBYTES

Reset

R/WRR

NumberofbytesinTXFIFODescription

SWRS040CPage83of

CC25000x3B(0xFB):RXBYTES–UnderflowandNumberofBytes

Bit76:0

FieldName

RXFIFO_OVERFLOWNUM_RXBYTES

Reset

R/WRR

NumberofbytesinRXFIFODescription

0x3C(0xFC):RCCTRL1_STATUS–LastRCOscillatorCalibrationResult

Bit76:0

FieldNameReserved

RCCTRL1_STATUS[6:0]

Reset

R/WR0R

ContainsthevaluefromthelastrunoftheRCoscillatorcalibrationroutine.

ForusagedescriptionrefertoAN047[3].Description

0x3D(0xFC):RCCTRL0_STATUS–LastRCOscillatorCalibrationResult

Bit76:0

FieldNameReserved

RCCTRL0_STATUS[6:0]

Reset

R/WR0R

ContainsthevaluefromthelastrunoftheRCoscillatorcalibrationroutine.

ForusagedescriptionrefertoAN047[3].Description

SWRS040CPage84of

CC250033PackageDescription(QFN20)

33.1

RecommendedPCBLayoutforPackage(QFN20)

Figure30:RecommendedPCBLayoutforQFN20Package

Note:Thefigureisanillustrationonlyandnottoscale.Therearefive10mildiameterviaholesdistributedsymmetricallyinthegroundpadunderthepackage.SeealsotheCC2500EMreferencedesign[4].33.2

SolderingInformation

Therecommendationsforlead-freereflowinIPC/JEDEJ-STD-020Dshouldbefollowed.

SWRS040CPage85of

CC250034OrderingInformation

OrderableDevice

CC2500RTKR

Status(1)

Active

PackageType

QFN

PackageDrawing

RTK

Pins20

PackageQty

3000

EcoPlan(2)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

LeadFinish

CuNiPdAu

MSLPeakTemp(3)

LEVEL3-260C1YEAR

CC2500RTKActiveQFNRTK2092CuNiPdAuLEVEL3-260C1YEAR

OrderableEvaluationModuleCC2500-CC2550DKCC2500EMKDescription

CC2500_CC2550DevelopmentKitCC1101DevelopmentKitMinimumOrderQuantity

11Figure31:OrderingInformation

35References

[1]CC2500ErrataNotes(swrz002.pdf)[2]AN0322.4GHzRegulations(swra060.pdf)

[3]AN047CC1100/CC2500–Wake-On-Radio(swra126.pdf)[4]CC2500EMReferenceDesign1.0(swrr016.zip)

SWRS040C

Page86of

CC2500[5]SmartRFStudio(swrc046.zip)

[6]CC1100CC2500ExamplesLibraries(swrc021.zip)

[7]CC1100/CC1150DK&CC2500/CC2550DKDevelopmentKitExamples&LibrariesUser

Manual(swru109.pdf)[8]CC25XXFoldedDipoleReferenceDesign(swrc065.zip)[9]DN004FoldedDipoleAntennaforCCC25xx(swra118.pdf)

SWRS040CPage87of

CC250036GeneralInformation

36.1

RevisionSWRS040CSWRS040B

DocumentHistory

Date2008-05-042007-05-09

Description/Changes

Updatedpackageandorderinginformation.

kbpsreplacedbykBaudthroughoutthedocument.

Someofthesectionshavebeenre-writtentobeeasiertoreadwithouthavinganynewinfoadded.Absolutemaximumsupplyvoltageratingincreasedfrom3.6Vto3.9V.FSKchangedto2-FSKthroughoutthedocument.UpdatestotheAbbreviationtable.

UpdatestotheElectricalSpecificationssection.AddedACP,OBWandblockingperformance.Maximumoutputpowerchangedfrom0dBmto+1dBm.

Addedinformationaboutreducedlinkperformanceatn/2∙crystalfrequency.AddedinfoaboutRXandTXlatencyinserialmode.

ChangestothemaximumRCoscillatorfrequencyaccuracyaftercalibration.

AddedinfoaboutdefaultvaluesafterresetversusoptimumregistersettingsintheConfigurationSoftwaresection.

ChangestotheSPIInterfaceTimingRequirements.Infoaddedabouttsp,pd

Thefollowingfigureshavebeenchanged:ConfigurationRegistersWriteandReadOperations,SRESCommandStrobe,andRegisterAccessTypes.

IntheRegisterAccesssection,theaddressrangeischanged.ChangestoPATABLEAccesssection.

InthePacketFormatsection,preamblepatternischangedto10101010andinfoaboutbugrelatedtoturningoffthetransmitterininfinitepacketlengthmodeisadded.AddedinfototheFrequencyOffsetCompensationsection.

AddedinfoabouttheinitialvalueofthePN9sequenceintheDataWhiteningsection.

AddedinfoaboutTXFIFOunderflowstateinthePacketHandlinginTransmitModesection.AddedsectionPacketHandlinginFirmware.

InthePQTsectionachangeismadeastohowmuchthecounterdecreases.TheRSSIvalueisindBmandnotdB.

ThewholeCSAbsoluteThresholdsectionhasbeenre-writtenandtheequationcalculatingthethresholdhasbeenremoved.

AddedinfointheCCAsectiononwhathappensifthechannelisnotclear.AddedinfototheLQIsectionforbetterunderstanding.

RemovedallreferencestothevoltageregulatorinrelationwiththeCHP_RDYnsignal,asthissignalisonlyrelatedtothecrystal.

Removedreferencestothevoltageregulatorinthefigures:Power-OnResetandPower-OnResetwithSRES.ChangestotheSIlineinthePower-OnResetwithSRESfigure.Addedinfoonthethreeautomaticcalibrationoptions.

AddedinfoaboutminimumsleeptimeandreferencestoApp.Note047togetherwithinfoaboutcalibrationoftheRCoscillator.

ThefigureEvent0andEvent1Relationshipischangedforbetterreadability.

InfoaddedtotheRCOscillatorandTimingsectionrelatedtoreducedcalibrationtime.

TheOutputPowerProgrammingsectionhasbeenchanged.Only1PATABLEentryusedfor2-FSK/GFSK/MSKand2PATABLEentriesusedforOOK.AddedinfoaboutPATABLEwhenenteringSLEEPmode.NewPA_POWERandPATABLEfigure.AddedsectiononPCBLayoutRecommendations.

InsectionGeneralPurpose/TestOutputControlPins:AddedinfoonGDOpinsinSLEEPstate.Asynchronoustransparentmodeiscalledasynchronousserialmodethroughoutthedocument.RemovedcommentsabouthavingtouseNRZcodinginsynchronousserialmode.AddedinfothatManchesterencodingcannotbeusedinasynchronousserialmode.Changednumberofcommandsstrobesfrom14to13.

Addedtwonewregisters;RCCTRL1_STATUSandRCCTRL0_STATUSChangedfieldnameand/ordescriptionofthefollowingregisters:

MCSM2,MCSM0,WORCTRL,FSCAL3,FSCAL2,FSCAL1,TEST2,TEST1andTEST0.Addedreferences.

SWRS040CPage88of

CC2500Revision

1.2SWRS040A

Date2006-06-28

Description/Changes

AddedfigurestotableonSPIinterfacetimingrequirements.AddedinformationaboutSPIread.

Updatestotextandincludednewfigureinsectiononarbitrarylengthconfiguration.UpdatestosectiononCRCcheck.AddedinformationaboutCRCcheckwhenPKTCTRL0.CC2400_EN=1.

AddedinformationonRSSIupdaterateinsectionRSSI.

Updatestotextandincludednewfiguresinsectiononpower-onstart-upsequence.Changestowake-on-radiocurrentconsumptionfiguresunderelectricalspecifications.UpdatestotextinsectionondataFIFO.

AddedinformationabouthowtocheckforPLLlockinsectiononVCO.

BetterexplanationofsomeofthesignalsintableofGDOsignalselection.Alsoaddedsomemoresignals.

Addedsectiononwidebandmodulationnotusingspreadspectrumundersectiononsystemconsiderationsandguidelines.

ChangestotimeoutforsyncwordsearchinRXinregisterMCSM2.

Changestowake-on-radiocontrolregisterWORCTRL.WOR_RES[1:0]settings10band11bchangedtoNotApplicable(NA).

AddedmoredetailedinformationonPO_TIMEOUTinregisterMCSM0.

AddeddescriptionofprogrammingbitsinregistersFOCCFG,BSCFG,AGCCTRL0,FREND1.Changestoorderinginformation.

MDMCFG2[7]used.26-27MHzcrystalrange.Chapter15:descriptionofthe2optionalappendbytes.Addedmatchinginformation.Addedinformationaboutusingareferencesignalinsteadofacrystal.CRCcanonlybecheckedbyappendbytesorCRC_AUTOFLUSH.AddedequationforcalculatingRSSIindBm.Selectivityperformancegraphsadded.Firstpreliminaryrelease.

1.12005-10-20

1.02005-01-24

Table38:DocumentHistory

SWRS040CPageof

PACKAGEOPTIONADDENDUM

www.ti.com

8-Dec-2009

PACKAGINGINFORMATION

OrderableDeviceCC2500-RTR1CC2500-RTY1CC2500RTKCC2500RTKG3CC2500RTKRCC2500RTKRG3

(1)

Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE

PackageTypeVQFNVQFNVQFNVQFNVQFNVQFN

PackageDrawingRTKRTKRTKRTKRTKRTK

PinsPackageEcoPlan(2)

Qty202020202020

3000Green(RoHS&

noSb/Br)929292

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

MSLPeakTemp(3)Level-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HRLevel-3-260C-168HR

3000Green(RoHS&

noSb/Br)3000Green(RoHS&

noSb/Br)

Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.

PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.

ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.

InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.

Addendum-Page1

PACKAGEMATERIALSINFORMATION

www.ti.com

8-Dec-2009

TAPEANDREELINFORMATION

*Alldimensionsarenominal

Device

PackagePackagePinsTypeDrawingVQFN

RTK

SPQ

ReelReelA0DiameterWidth(mm)(mm)W1(mm)330.0

12.4

4.3

B0(mm)4.3

K0(mm)1.5

P1(mm)8.0

WPin1(mm)Quadrant12.0

CC2500RTKR3000

PackMaterials-Page1

PACKAGEMATERIALSINFORMATION

www.ti.com

8-Dec-2009

*Alldimensionsarenominal

DeviceCC2500RTKR

PackageType

VQFN

PackageDrawing

RTK

Pins20

SPQ3000

Length(mm)

378.0

Width(mm)

70.0

Height(mm)

346.0

PackMaterials-Page2

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