DATA SHEET
DS07-12504-5E
8-bit Proprietary MicrocontrollerCMOS
FMC-8L MB89860/850 Series
2
MB89865/867/P867/W867MB89855/857/P857/W857/T855
sDESCRIPTION
The MB89860/850 series has been developed as a general-purpose version of the F2MC*-8L family consistingof proprietary 8-bit, single-chip, microcontrollers.
In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollerscontain a variety of peripheral functions such as a timer unit, PWM timers, a UART, a serial interface, a 10-bit A/D converter, and an external interrupt.
The MB89860/850 series is applicable to a wide range of applications from welfare products to industrialequipment, including portable devices.
*: F2MC stands for FUJITSU Flexible Microcontroller.
sFEATURES
•Various package options
QFP package (80 pins): MB89860SDIP package (64 pins): MB89850•High-speed processing at low voltage
Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V
(Continued)sPACKAGE
80-pin Ceramic QFP64-pin Plastic SH-DIP80-pin Plastic QFP64-pin Plastic SH-DIP(FPT-80P-M06)(DIP-64P-M01)(FPT-80C-A02)(DIP-64C-A06)MB89860/850 Series
(Continued)•F2MC-8L family CPU core
Instruction set optimized for controllers
Multiplication and division instructions16-bit arithmetic operationsTest and branch instructions
Bit manipulation instructions, etc.
•8-bit PWM timers: 2 channelsAlso usable as a reload timer•UART
Full-duplex double buffer
Synchronous and asynchronous data transfer•8-bit serial I/O
Switchable transfer direction allows communication with various equipment.•10-bit A/D converter
Conversion time: 13.2 µs
Activation by an external input or a timer unit capable•External interrupt: 4 channels
Four channels are independent and capable of wake-up from low-power consumption modes (with an edgedetection function).
•Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)•Bus interface functions
Including hold and ready functions•Timer unit
Outputs non-overlap three-phase waveforms to control an AC inverter motor.Also usable as a PWM timer (4 channels)
2
MB89860/850 Series
sPRODUCT LINEUP
Part number
Parameter
MB89855MB89T855
MB89865MB89857MB89867
MB89P857MB89W857MB89P867MB89W867
Classification
Mass production products (mask ROM products)
ROM size
16 K × 8 bits
(internal mask ROM)Note: In MB89T855, no
internal ROM can be used but external ROM is used.
One-time PROM pruducts/EPROM products, also used for evaluation
32 K × 8 bits
(internal PROM,
programming with general-purpose EPROM programmer)
32 K × 8 bits (internal mask ROM)
RAM sizeCPU functions
512 × 8 bits
Number of instructions: Instruction bit length: Instruction length: Data bit length:
Minimum execution time: Interrupt processing time:
1 K × 8 bits
1368 bits
1 to 3 bytes1, 8, 16 bits0.4 µs/10 MHz3.6 µs/10 MHz
Ports
Input ports: 5 (All also serve as peripherals)Output ports (N-ch open drain): 8 (All also serve as peripherals)I/O ports (N-ch open drain): 15 (MB89860 series only)Output ports (CMOS): 8 (All also serve as bus control pins)I/O ports (CMOS): 32 (All also serve as bus pins or peripherals)Total: 68 (53 pins for MB89850 series)
10-bit up/down count timer × 1
Compare registers with buffer × 4
Compare timer unit clear register with buffer × 1
Zero detection pin control
4 output channels
Non-overlap three-phase waveform outputIndependent three-phase dead-time timer
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to
25.6 µs)
8-bit resolution PWM operation (conversion cycle: 102 µs to 6.528 ms)
8 bits
Clock synchronous/asynchronous data transfer capable
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
10-bit resolution × 8 channelsA/D conversion time: 13.2 µs
Continous activation by a compare channel 0 in timer unit or an external activation capable
Timer unit
8-bit PWM timer 1,8-bit PWM timer 2UART8-bit serial I/O
10-bit A/D converter
External interrupt
4 independent channels (edge selection, interrupt vector, source flag)
Rising edge/falling edge selectability.
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby modesProcess
Operating voltage*
Sleep mode, stop mode
CMOS
2.7 V to 6.0 V
2.7 V to 5.5 V
* :Varies with conditions such as the operating frequency. (See section “s Electrical Characteristics.”)
3
MB89860/850 Series
sPACKAGE AND CORRESPONDING PRODUCTS
Package DIP-64P-M01DIP-64C-A06FPT-80P-M06FPT-80C-A02
×××
××
×
MB89855MB89T855MB89857MB89P857
MB89W857
×
MB89865MB89867MB89P867
××
MB89W867
×××
: Available × : Not available
Note:For more information about each package, see section “s Package Dimensions.”
sDIFFERENCES AMONG PRODUCTS
1.Memory Size
Before evaluating using the OTPROM (one-time PROM) products (also used for evaluation), verify its differencesfrom the product that will actually be used.Take particular care on the following point:
•The stack area, etc., is set at the upper limit of the RAM.
2.Current Consumption
When operated at low speed, the product with an OTPROM or an EPROM will consume more current than theproduct with a mask ROM.
However, the current consumption in sleep/stop modes is the same.
3.Mask Options
In the MB89P857/W857/P867/W867/T855, no option can be set.Before using options check section “s Mask Options.”Take particular care on the following point:
•A pull-up resistor can be set for P00 to P07, P10 to P17 and P20 to P27 only at single-chip mode.
4
MB89860/850 Series
sPIN ASSIGNMENT
(Top view)P31/SO1P30/SCK1P47/TRGIP46/ZP45/YP44/XP43/RTO3/WP42/RTO2/VP41/RTO1/UP40/RTO0P50/AN0P51/AN1P52/AN2P53/AN3P54/AN4P55/AN5P56/AN6P57/AN7AVCCAVRAVSSP64/DTTIP63/INT3/ADSTP62/INT2P61/INT1P60/INT0RSTMOD0MOD1X0X1VSS1234567891011121314151617181920212223242526272829303132(DIP-64P-M01)(DIP-64C-A06)6463626160595857565554535251504948474645444342414039383736353433VCCP32/SI1P33/SCK2P34/SO2P35/SI2P36/PTO1P37/PTO2VSSP00/AD0P01/AD1P02/AD2P03/AD3P04/AD4P05/AD5P06/AD6P07/AD7P10/A08P11/A09P12/A10P13/A11P14/A12P15/A13P16/A14P17/A15P20/BUFCP21/HAKP22/HRQP23/RDYP24/CLKP25/WRP26/RDP27/ALE5
MB89860/850 Series
(Top view)P83AVSSAVRAVCCP57/AN7P56/AN6P55/AN5P54/AN4P53/AN3P52/AN2P51/AN1P50/AN0P84P85P86P87P82P81P80P76P75P74P73P72P71P70MOD0MOD1X0X1VSSRSTP27/ALEP26/RDP25/WRP24/CLKP23/RDYP22/HRQP21/HAKP20/BUFC8079787776757473727170696867666512345678910111213141516171819202122232425262728293031323334353637383940646362616059585756555453525150494847464544434241N.C.P40/RTO0P41/RTO1/UP42/RTO2/VP43/RTO3/WP44/XVSSP45/YP46/ZVCCP47/TRGIP60/INT0P61/INT1P62/INT2P63/INT3/ADSTP64/DTTIP30/SCK1P31/SO1P32/SI1P33/SCK2P34/SO2P35/SI2P36/PTO1P37/PTO26
P17/A15P16/A14P15/A13P14/A12P13/A11P12/A10P11/A09P10/A08P07/AD7P06/AD6P05/AD5P04/AD4P03/AD3P02/AD2P01/AD1P00/AD0(FPT-80P-M06)(FPT-80C-A02)MB89860/850 Series
sPIN DESCRIPTION
Pin no.
SH-DIP*1
3031282927
QFP*21314111216
Pin nameX0X1MOD0MOD1RSTCB
Operating mode selection pinsConnect directly to VCC or VSS.
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”.
General-purpose I/O ports
When an external bus is used, these ports function as multiplex pins of lower address output and data I/O.General-purpose I/O ports
When an external bus is used, these ports function as upper address output.
General-purpose output port
When an external bus is used, this port can also be used as a buffer control output.
General-purpose output port
When an external bus is used, this port can also be used as a hold acknowledge output.
General-purpose output port
When an external bus is used, this port can also be used as a hold request input.
General-purpose output port
When an external bus is used, this port functions as a ready input.
General-purpose output port
When an external bus is used, this port functions as a clock output.
General-purpose output port
When an external bus is used, this port functions as a write signal output.
General-purpose output port
When an external bus is used, this port functions as a read signal output.
General-purpose output port
When an external bus is used, this port functions as an address latch signal output.
General-purpose I/O port
Also serves as the clock I/O for the UART.This port is a hysteresis input type.
Circuit typeA
Function
Crystal oscillator pins (10 MHz)
56 to 4940 to 33
P00 /AD0 toP07/AD7P10 /A08 toP17/A15P20/BUFC
D
48 to 4132 to 25D
4024F
3923P21/HAKF
3822P22/HRQD
3721P23/RDYD
3620P24/CLKF
3519P25/WRF
3418 P26/RDF
3317P27/ALEF
248P30/SCK1E
*1:DIP-64P-M01, DIP-64C-A06*2:FPT-80P-M06, FPT-80C-A02
(Continued)7
MB89860/850 Series
(Continued)Pin no.
SH-DIP*1
1
QFP*247
Pin nameP31/SO1
Circuit typeE
Function
General-purpose I/O port
Also serves as the data output for the UART.This port is a hysteresis input type.General-purpose I/O port
Also serves as the data input for the UART.This port is a hysteresis input type.
General-purpose I/O port
Also serves as the clock I/O for the 8-bit serial I/O.This port is a hysteresis input type.
General-purpose I/O port
Also serves as the data output for the 8-bit serial I/O.This port is a hysteresis input type.
General-purpose I/O port
Also serves as the data input for the 8-bit serial I/O.This port is a hysteresis input type.
General-purpose I/O port
Also serves as the pulse output for the 8-bit PWM timer 1.This port is a hysteresis input type.
General-purpose I/O port
Also serves as the pulse output for the 8-bit PWM timer 2.This port is a hysteresis input type.
General-purpose I/O port
Also serves as the pulse output for the timer unit.This port is a hystereisis input type.
General-purpose I/O ports
Also serve as the pulse output for the timer unit or a non-overlap three-phase waveform output.These ports are a hysteresis input type.General-purpose I/O ports
Also serve as a non-overlap three-phase output.These ports are a hysteresis input type.
General-purpose I/O port
Also serves as the trigger input for the timer unit.This port is a hysteresis input type.
N-ch open-drain output ports
Also serve as the analog input for the A/D converter.General-purpose input ports
Also serve as an external interrupt input.These ports are a hysteresis input type.
General-purpose input port
Also serves as an external interrupt input and as the activation trigger input for the A/D converter.This port is a hysteresis input type.
6346P32/SI1E
6245P33/SCK2E
6144P34/SO2E
6043P35/SI2E
5942P36/PTO1E
5841P37/PTO2E
1063P40/RTO0E
9, 8,7 6, 5,43
62, 61,60 59, 57,5654
P41/RTO1/U,P42/RTO2/V,P43/RTO3/WP44/X,P45/Y,P46/ZP47/TRGI
E
E
E
11 to 1826 to 24
69 to 7653 to 51
P50/AN0 to P57/AN7P60/INT0 to P62/INT2P63/INT3/ADST
HI
2350I
*1:DIP-64P-M01, DIP-64C-A06*2:FPT-80P-M06, FPT-80C-A028
(Continued)MB89860/850 Series
(Continued)Pin no.
SH-DIP*1
22
QFP*249
Pin nameP64/DTTI
Circuit typeI
Function
General-purpose input port
Also serves as a dead-time timer disable input.This port is a hysteresis input type.DTTI input is with a noise canceller.N-ch open-drain I/O ports
These ports are a hysteresis input type.N-ch open-drain I/O ports
These ports are a hysteresis input type.Power supply pinPower supply (GND) pinsA/D converter power supply pin
A/D converter reference voltage input pinA/D converter power supply (GND) pinUse this pin at the same voltage as VSS.Internally connected pinBe sure to leave it open.
——6432, 57192021—
10 to 43 to 1, 80,68 to 65
5515, 5877787964
P70 to P76P80 to P87VCCVSSAVCCAVRAVSSN.C.
GG——————
*1:DIP-64P-M01, DIP-64C-A06*2:FPT-80P-M06, FPT-80C-A02
9
MB89860/850 Series
sI/O CIRCUIT TYPE
TypeACircuitRemarks•At an oscillation feedback resitor of approximately X11 MΩ/5.0 VX0 Standby control signalBCRP-ch•At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V•Hysteresis inputN-chDRP-chP-ch•CMOSoutput•CMOSinputN-ch•Pull-up resistor optional (Mask ROM products)•At a pull-up resistor of approximately 50 kΩ/5.0 VERP-chP-ch•CMOSoutput•Hysteresis inputN-ch•Pull-up resistor optional (Mask ROM products)•At a pull-up resistor of approximately 50 kΩ/5.0 V(Continued)10
MB89860/850 Series
(Continued) TypeFRP-chP-chCircuit•CMOSoutputRemarksN-ch•Pull-up resistor optional (Mask ROM products)•At a pull-up resistor of approximately 50 kΩ/5.0 V•N-ch open-drain output•Hysteresis inputGRP-chP-chN-ch•Pull-up resistor optional (Mask ROM products)•At a pull-up resistor of approximately 50 kΩ/5.0 VH•N-ch open-drain output •Analog inputP-chN-ch Analog inputIR•Hysteresis input•Pull-up resistor optional (Mask ROM products)•At a pull-up resistor of approximately 50 kΩ/5.0 V11
MB89860/850 Series
sHANDLING DEVICES
1.Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pinsother than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute MaximumRatings” in section “s Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. Whenusing, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digitalpower supply (VCC) when the analog system power supply is turned on and off.
2.Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-downresistor.
3.Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4.Treatment of N.C. Pin
Be sure to leave (internally connected) N.C. pin open.
5.Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltagecould cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is thereforeimportant. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-Pvalue) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transientfluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6.Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) andwake-up from stop mode.
12
MB89860/850 Series
sPROGRAMMING TO THE EPROM ON THE MB89P867/W867/P857/W857
The MB89P867/W867/P857/W857 are an OTPROM version of the MB89860/850 series.
1.Features
•32-Kbyte PROM on chip
•Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2.Memory Space
Memory space in EPROM mode is diagrammed below.
Address0000HSingle chipI/O EPROM mode ( Corresponding addresses on the EPROM programmer)0080HRAM0480HNot available8000H0000HPROM32 KBEPROM32 KBFFFFH7FFFH3.Programming to the EPROM
In EPROM mode, the MB89P867/W867/P857/W857 functions equivalent to the MBM27C256A. This allows thePROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannotbe used) by using the dedicated socket adapter.•Programming procedure
(1)Set the EPROM programmer to the MBM27C256A.
(2)Load program data into the EPROM programmer at 0000H to 7FFFH (note that addresses 8000H to FFFFH
while operating as a single chip assign to addresses 0000H to 7FFFH in EPROM mode.)(3)Program to 0000H to 7FFFH with the EPROM programmer.
13
MB89860/850 Series
4.Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blankedOTPROM microcomputer program.
Program, verifyAging+150°C, 48 Hrs.Data verificationAssembly5.Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.For this reason, a programming yield of 100% cannot be assured at all times.
6.Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to anultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. Thisdosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensityof 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and allfilters should be removed from the UV light source prior to erasure.
It is important to note that the internal EPROM and similar devices, will erase with light sources havingwavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, andexposure to them should be prevented to realize maximum system reliability. If used in such an environment,the package windows should be covered by an opaque label or substance.
7.EPROM Programmer Socket Adapter
PackageDIP-64P-M01FPT-80P-M01
Compatible socket adapterROM-64SD-28DP-8L*ROM-80QF-28DP-8L2
* :Connect the adapter jumper pin to VSS when using.Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
14
MB89860/850 Series
sBLOCK DIAGRAM
X0X1OscillatorTime-base timerClock controller8-bit PWM timer 2P37/PTO2RSTReset circuit (WDT)8-bit PWM timer 1P36/PTO18-bit serial I/O Port 0 and port 1CMOS I/O portInternal busP00/AD0 to P07/AD7P10/A08 to P17/A15MOD0MOD1P27/ALEP26/RDP25/WRP24/CLKP23/RDYP22/HRQP21/HAKP20/BUFC8P35/SI2P34/SO2P33/SCK2P32/SI1P31/SO1P30/SCK18UARTExternal bus interfaceCMOS I/O portCMOS I/O portPort 2Port 4Port 36Timer unitCMOS output port(Dead-time timer)P47/TRGIP46/ZP45/YP44/XP43/RTO3/WP42/RTO2/VP41/RTO1/UP40/RTO0P64/DTTI4External interrupt3P60/INT0to P62/INT2P63/INT3/ADSTInput portAVRAVCCAVSSPort 510-bit A/D converter88P50/AN0to P57/AN7RAMF2MC-8LCPUROMOther pinsVCC, VSS × 2Part numberMB89865/855/T855*1MB89857/867MB89W857/P867RAM size512 bytes1 Kbyte1 KbyteROM size16 Kbytes32 Kbytes32 Kbytes(EPROM)N-ch open-drain output port*2P70 to P768P80 to P87Port 67N-ch open-drain I/O portPort 7 and port 8*1: In the MB89T855, an external ROM can be used.*2: Not included in the MB89850 series.15
MB89860/850 Series
sCPU CORE
1.Memory Space
The microcontrollers of the MB89860/850 series offer a memory space of 64 Kbytes for storing all of I/O, data,and program areas. The I/O area is located at the lowest address. The data area is provided immediately abovethe I/O area. The data area can be divided into register, stack, and direct areas according to the application.The program area is located at exactly the opposite end, that is, near the highest address. Provide the tablesof interrupt reset vectors and vector call instructions toward the highest address within the program area. Thememory space of the MB89860/850 series is structured as illustrated below.Memory SpaceMB89865MB89855/T855*20000HI/O0080HRAM512 B0100HRegister0200H0280H0200H0480HExternal areaExternal area8000H0100HRegister0080HRAM1 KB0000HI/OMB89867/857MB89W867/P867MB89W857/P857C000HROM*16 KBFFFFH1ROM*32 KB1FFFF H*1: The ROM area is an external area depending on the mode.*2: In the MB89T855, an external ROM can be used.16
MB89860/850 Series
2.Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registersin the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When theinstruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.Index register (IX):Extra pointer (EP): Stack pointer (SP): Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
Initial value: Program counter: Accumulator: Temporary accumulator: Index register: Extra pointer: Stack pointer: Program statusFFFDHUndefinedUndefinedUndefinedUndefinedUndefinedI-flag = 0, IL1, 0 = 11Other bits are undefined.16 bitsPCATIXEPSPPSThe PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits foruse as a condition code register (CCR). (See the diagram below.)Structure of the Program Status Register15PS1413RP121110987H6I543N2Z1V0CVacancyVacancyVacancyIL1, 0RPCCR17
MB89860/850 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contentsand the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register AreaRPLower OP codesb1↓b0↓“0”“0”“0”“0”“0”“0”“0”“1”R4R3R2R1R0b2↓↓↓↓↓↓↓↓↓↓↓↓↓↓Generated addressesA15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data andbits for control of CPU operations at the time of an interrupt.
H-flag:Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions. I-flag:IL1, 0:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0when reset.
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level ishigher than the value indicated by this bit.
IL10011
IL00101
Interrupt level
123
Low = no interrupt
High-low High
N-flag:Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag:V-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow doesnot occur.
C-flag:Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
18
MB89860/850 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank containseight registers and up to a total of 32 banks can be used on the MB89860/850 series. The bank currently in useis indicated by the register bank pointer (RP).
Note:The number of register banks that can be used varies with the RAM size. Register Bank ConfigurationThis address = 0100H + 8 × (RP)R 0R 1R 2R 3R 4R 5R 6R 732 banksMemory area19
MB89860/850 Series
sI/O MAP
Address00H01H02H03H04H05H06H07H08H09H0AH0BH0CH0DH0EH0FH10H11H12H13H14H15H16H17H to 1BH
1CH1DH1EH1FH20H21H22H23H24H25H
(R/W)(W)(R/W)(W)(R/W)(R/W)(R/W)(R/W)(R/W)(R/W)
CTR1CMR1CTR2CMR2SMCSRCSSDSIDR/SODR
SMRSDR
(R/W)
PDR8
(R/W)
PDR7
(R)
PDR6
(R/W)(W)(R/W)(W)(R/W)
PDR3DDR3PDR4DDR4PDR5
(R/W)(W)(R/W)
STBCWDTCTBTC
Read/write(R/W)(W)(R/W)(W)(R/W)(W)
Register name
PDR0DDR0PDR1DDR1PDR2BCTR
Register description
Port 0 data register
Port 0 data direction registerPort 1 data register
Port 1 data direction registerPort 2 data register
External bus pin control registerVacancyVacancy
Standby control registerWatchdog timer control registerTime-base timer control registerVacancy
Port 3 data register
Port 3 data direction registerPort 4 data register
Port 4 data direction registerPort 5 data registerVacancy
Port 6 data registerVacancy
Port 7 data registerVacancy
Port 8 data registerVacancy
PWM control register 1PWM compare register 1PWM control register 2PWM compare register 2UART serial mode control registerUART serial rate control registerUART serial status/data registerUART serial data registerSerial mode registerSerial data register
(Continued)20
MB89860/850 Series
(Continued)
Address26H27H28H29H2AH2BH2CH2DH2EH2FH30H31H32H33H34H35H36H37H38H39H3AH3BH3CH3DH3EH3FH40H to 7BH
7CH7DH7EH7FH
(W)(W)(W)
ILR1ILR2ILR3
(W)(W)(W)(R/W)(R/W)(R/W)(R/W)(R/W)(R/W)(W)(R/W)(W)(W)(W)(W)(W)(W)(W)(W)
ZOCTRCLRBRHCLRBRLTCSRCICRTMCRCOERCMCRDTCRDTSROCTBROCPBR0HOCPBR0LOCPBR1HOCPBR1LOCPBR2HOCPBR2LOCPBR3HOCPBR3L
Read/write(R/W)(R/W)(R/W)(R/W)(R)(R)
Register name
EIC1EIC2ADC1ADC2ADDHADDL
Register description
External interrupt control register 1External interrupt control register 2A/D converter control register 1A/D converter control register 2A/D converter data register (H)A/D converter data register (L)Vacancy
Zero detection output control registerCompare clear buffer register (H)Compare clear buffer register (L)Timer control status registerCompare interrupt control registerTimer mode control registerCompare/port selection registerCompare buffer mode control registerDead-time timer control registerDead-time setting registerOutput control buffer registerOutput compare buffer register 0 (H)Output compare buffer register 0 (L)Output compare buffer register 1 (H)Output compare buffer register 1 (L)Output compare buffer register 2 (H)Output compare buffer register 2 (L)Output compare buffer register 3 (H)Output compare buffer register 3 (L)Vacancy
Interrupt level setting register 1Interrupt level setting register 2Interrupt level setting register 3Vacancy
Notes:•Do not use vacancies.
•When a read-modify-write instruction (such as bit set) is used to access a write-only register or a registercontaining a write-only bit, a bit designated by the instruction will have a predetermined value. However,a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. So no accessto the register should be tried with any read-modefy-write instruction.
21
MB89860/850 Series
sELECTRICAL CHARACTERISTICS
1.Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltageA/D converter reference input voltage
Program voltageInput voltageOutput voltage
“L” level maximum output current
SymbolVCCAVCCAVRVPPVIVOIOLIOLAV1IOLAV2ΣIOLAV1ΣIOLAV2
“H” level maximum output currentIOH“H” level average output current“H” level total maximum output current
Power consumptionOperating temperatureStorage temperature
IOHAVΣIOHPDTATstg
ValueMin.VSS – 0.3VSS – 0.3VSS – 0.3VSS – 0.3VSS – 0.3—————————–40–55
Max.VSS + 7.0VSS + 7.013.0VCC + 0.3VSS + 0.3204153050–20–4–20300+85+150
UnitVVVVVmAmAmAmAmAmAmAmAmW°C°C
P00 to P07, P10 to P17,P20 to P27, P30 to P37,P50 to P57, P70 to P76,P80 to P87P40 to P47
P00 to P07, P10 to P17,P20 to P27, P30 to P37,P50 to P57, P70 to P76,P80 to P87P40 to P47*
AVR must not exceed AVCC + 0.3 V.
MOD1 pins of MB89P867/W867 and MB89P857/W857
Remarks
“L” level average output current
“L” level total average output current
*:Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
Precautions:Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections ofthis data sheet. Exposure to absolute maximum rating conditions for extended periods may affectdevice reliability.
22
MB89860/850 Series
2.Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
ValueMin.2.7*
VCCAVCC
Max.6.0*
Unit
Remarks
Normal operation assurance range*
MB89867/865, MB89857/855Normal operation assurance range*
MB89P867/W867,
MB89P857/W855/T855Retains the RAM state in stop mode
V
Power supply voltage
2.7*5.5*V
1.5
A/D converter reference input voltage
Operating temperature
AVRTA
0.0–40
6.0AVCC+85
VV°C
*:These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and “5. A/D Converter Electrical Characteristics.”Note:Connect the MOD0 and MOD1 pins to VCC or VSS.
65.55Operation assurance rangeOperating voltage (V)Analog accuracy assured in theVCC = AVCC = 3.5 V to 6.0 V range432112345678910Clock operating frequency (MHz)(µs)4.02.00.80.4Minimum execution time (instruction cycle)Note: The shaded area is assured only for the MB89865/867/855/857.Figure 1 Operating Voltage vs. Clock Operating Frequency
23
MB89860/850 Series
3.DC Characteristics
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
SymbolVIH
“H” level input voltage
VIHSVIL
“L” level input voltage
VILSVOH
Pin
P00 to P07, P10 to P17,P22, P23
RST, P30 to P37,
P40 to P47, P60 to P64,P70 to P76, P80 to P87P00 to P07, P10 to P17,P22, P23
RST, P30 to P37,
P40 to P47, P60 to P64,P70 to P76, P80 to P87
Condition
————
Value
Min.0.7VCC0.8VCCVSS – 0.3VSS – 0.32.4
Typ.—————
Max.VCC + 0.3VCC + 0.30.3 VCC0.2 VCC
—
UnitVVVVV
Remarks
“H” level output voltage“L” level output voltage
P00 to P07, P10 to P17,IOH = –2.0 P20 to P27, P30 to P37,
mAP40 to P47
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P70 to P76,IOL = 1.8 mAP80 to P87
VOL1VOL2
————
0.41.5±5
VVµA
With pull-up resistor
P40 to P47IOL = 15 mA
Input leackage current
Pull-up resistance
ILI1
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,0.0 V < VI <
P40 to P47, P60 to P64,—
P70 to P76, P80 to P87,VCCMOD0, MOD1
— RPULLRSTVI = 0.0 VFC = 10 MHzNormal operation mode(External clock)
2550100kΩ
ICC—1518mA
VCC
Power supply current
ICCS
FC = 10 MHzSleep mode(External clock)Stop modeTA = +25°C
—68mA
ICCH——10µA
IAAVCC
Other than AVCC, AVSS, VCC, and VSS
FC = 10 MHz, when A/D conversion is activatedf = 1 MHz
—6—mA
Input capacitanceCIN—10—pF
24
MB89860/850 Series
4.AC Characteristics
(1)Reset Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
RST “L” pulse widthSymboltZLZH
Condition
—
ValueMin.16 tXCYL*
Max.—
Unitns
Remarks
* :tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.
t ZLZHRST0.2 VCC0.2 VCC(2)Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Power supply rising timePower supply cut-off time
SymboltRtOFF
Condition
ValueMin.—1
Max.50—
Unitmsms
Remarks
Power-on reset function onlyDue to repeated operations
—
Note:Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR2.0 V0.2 V 0.2 VtOFFVCC0.2 V25
MB89860/850 Series
(3)Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Clock frequencyClock cycle timeInput clock pulse width
SymbolFCtXCYLPWHPWL
PinX0, X1
—
X0
—
10
ns
External clock
Condition
ValueMin.110020
Max.101000—
UnitMHznsns
External clockRemarks
tCR
Input clock rising/falling time
tCF
X0 and X1 Timing ConditionstXCYLPWHtCR0.8 VCC0.8 VCC0.2 VCC0.2 VCCtCFPWLX00.2 VCC Clock ConditionsWhen a crystalor ceramic resonator is usedWhen an external clock is usedX0X1X0X1Open(4)Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
Symboltinst
Value (typical)
4/FC
Unitµs
Remarks
tinst = 0.4 µs when operating at FC = 10 MHz
26
MB89860/850 Series
(5)Recommended Resonator Manufacturers
Sample Application of Piezoelectric Resonator (FAR Series)X0X1FAR*C1C2*: Fujitsu Acoustic ResonatorC1 = C2 = 20 pF±8 pF (built-in FAR)FAR part number(built-in capacitor type)FAR-C4CB-08000-M02FAR-C4CB-10000-M02Inquiry: FUJITSU LIMITEDInitial deviation of FrequencyFAR frequency (TA = +25°C)8.00 MHz10.00 MHz±0.5%±0.5%Temperature characteristics of FAR frequency(TA = –25°C to +60°C)±0.5%±0.5%27
MB89860/850 Series
Sample Application of Ceramic ResonatorX0*X1C1C2Resonator manufacturer*Kyocera CorporationMurata Mfg. Co., Ltd.ResonatorKBR-7.68MWSKBR-8.0MWSCSA8.00MTZFrequency7.68 MHz8.0 MHz8.0 MHzC1 (pF)333330C2 (pF)333330R (kΩ)———Inquiry:Kyocera Corporation •AVX CorporationNorth American Sales Headquarters: TEL 1-803-448-9411•AVX LimitedEuropean Sales Headquarters: TEL 44-1252-770000•AVX/Kyocera H.K. Ltd.Asian Sales Headquarters: TEL 852-363-3303Murata Mfg. Co., Ltd.•Murata Electronics North America, Inc.: TEL 1-404-436-1300•Murata Europe Management GmbH: TEL 49-911-66870•Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-423328
MB89860/850 Series
(6)Clock Output Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
ParameterCycle timeCLK ↑ → CLK ↓
SymboltCYC
CLK
tCHCL
Pin
ConditionLoad condition:50 pF
ValueMin.20030
Max.—100
Unitnsns
RemarkstXCYL × 2 at 10 MHz oscillationApprox. tCYC/2 at 10 MHz oscillation
t CYCt CHCL2.4 V2.4 V0.8 VCLK29
MB89860/850 Series
(7)Bus Read Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
ParameterValid address → RD ↓ time
RD pulse widthValid address → data read time
RD ↓ → data read timeRD ↑ → data hold timeRD ↑ → ALE ↑ timeRD ↓ → CLK ↑ timeCLK ↓ → RD ↑ timeRD ↓ → BUFC ↓ timeBUFC ↑ → valid address time
SymboltAVRLtRLRHtAVDVtRLDVtRHDXtRHLHtRLCHtCLRHtRLBLtBHAV
Pin
RD, A15 to A08, AD7 to AD0
Condition
Value (10 MHz)Min.
1/4 tinst* – 64 ns1/2 tinst* – 20 ns
Max.——1/2tinst*
1/2 tinst* – 80 ns
Unitnsnsnsnsnsnsnsnsnsnsns
Remarks
RDAD7 to AD0, A15 to A08
RD, AD7 to AD0AD7 to AD0, RDLoad
——0
1/4 tinst* – 40 ns1/4 tinst* – 40 ns1/4 tinst* – 60 ns
NowaitNo wait
——————
—
RD, ALERD, A15 to A08RD ↑ → address invalid timetRHAX
condition:
50 pF
RD, CLKRD, BUFCA15 to A08, AD7 to AD0, BUFC
0–55
* :For information on tinst, see “(4) Instruction Cycle.”
CLK2.4 V0.8 VtRHLHALE0.8 VAD2.4 V0.8 VtAVDV0.7 VCC0.3 VCC0.7 VCC0.3 VCCtRHDX2.4 V0.8 VA2.4 V0.8 VtAVRLtRLCHtRLDVtRLRH2.4 VtCLRH0.8 VtRHAX2.4 V2.4 V0.8 VRD0.8 VtRLBLtBHAV2.4 VBUFC0.8 V30
MB89860/850 Series
(8)Bus Write Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
PinAD7 to AD0, ALE, A15 to A08WR, ALEWRAD7 to AD0, WRCondition
Value (10 MHz)Min.
1/4 tinst*1 – 64 ns
Max.————————————
Unitnsnsnsnsnsnsnsnsnsnsnsns
Remarks
Valid address → ALE ↓ timetAVLLALE ↓ time → address invalid time
Valid address → WR ↓ time
tLLAXtAVWLtWLWHtWHAXtWHLHtWLCHtCLWHtLHLLtLLCH
5
1/4 tinst*1 – 60 ns1/2 tinst*1 – 20 ns1/2 tinst*1 – 60 ns1/4 tinst*1 – 40 ns1/4 tinst*1 – 40 ns1/4 tinst*1 – 40 ns1/4 tinst*1 – 60 ns
WR pulse widthWR ↑ → address invalid time
Write data → WR ↑ timetDVWHWR ↑ → data hold timetWHDXWR ↑ → ALE ↑ timeWR ↓ → CLK ↑ timeCLK ↓ → WR ↑ timeALE pulse widthALE ↓ → CLK ↑ time
Load condition:
AD7 to AD0, WR50 pF
WR, A15 to A08
WR, ALEWR, CLKALEALE, CLK
0tXCYL – 35 ns*2tXCYL – 35 ns*2
*1:For information on tinst, see “(4) Instruction Cycle.”
*2:These characteristics are also applicable to the bus read timing.
CLKtLHLLtLLCH2.4 V0.8 Vt WHLH0.8 VtAVLLtLLAX2.4 V0.8 VtDVWH2.4 V0.8 VtWHDX2.4 VtCLWH0.8 VtWHAXtWLWH2.4 V0.8 V0.8 VALE2.4 VAD2.4 V2.4 V0.8 V0.8 VA2.4 V0.8 VtAVWL tWLCHWR31
MB89860/850 Series
(9)Ready Input Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
RDY valid → CLK ↑ timeCLK ↑ → RDY invalid time
SymboltYVCHtCHYX
PinRDY,CLK
ConditionLoad condition: 50 pF
ValueMin.600
Max.——
Unitnsns
Remarks
**
* :These characteristics are also applicable to the read cycle.
CLK2.4 V2.4 VALEADAddressDataAWRt YVCHt CHYX0.7 VCCRDY0.3 VCC0.3 VCCt YVCHt CHYX0.7 VCCNote:The bus cycle is also extended in the read cycle in the same manner.32
MB89860/850 Series
(10)UART and Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Serial clock cycle timeSCK1 ↓ → SO1 timeSCK2 ↓ → SO2 timeValid SI1 → SCK1 ↑ Valid SI2 → SCK2 ↑
SymboltSCYCtSLOVtIVSH
PinSCK1,SCK2SCK1, SO1SCK2, SO2SI1, SCK1SI2, SCK2SCK1, SI1SCK2, SI2SCK1, SCK2SCK1, SO1SCK2, SO2SI1, SCK1SI2, SCK2SCK1, SI1SCK2, SI2
External shift clock mode Load
condition: 50 pFInternal shift clock mode Load
condition: 50 pFCondition
ValueMin.2 tinst*–2001/2 tinst*1/2 tinst*1 tinst*1 tinst*01/2 tinst*1/2 tinst*
Max.—200————200——
Unitµsnsµsµsµsµsnsµsµs
Remarks
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold timetSHIXSerial clock “H” pulse widthSerial clock “L” pulse width
tSHSLtSLSHtSLOVtIVSH
SCK1 ↓ → SO1 timeSCK2 ↓ → SO2 timeValid SI1 → SCK1 ↑ Valid SI2 → SCK2 ↑
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold timetSHIX
* :For information on tinst, see “(4) Instruction Cycle.”
33
MB89860/850 Series
Internal Shift Clock ModetSCYCSCK1SCK20.8 V 2.4 V0.8 V tSLOVSO1SO22.4 V 0.8 V tIVSHtSHIX0.8 VCC0.2 VCCSI1SI20.8 VCC0.2 VCCExternal Shift Clock Modet SLSHt SHSLSCK1SCK20.2 VCC0.2 VCC0.8 VCC0.8 VCCt SLOVSO1SO22.4 V 0.8 V tIVSHtSHIX0.8 VCC0.2 VCCSI1SI20.8 VCC0.2 VCC34
MB89860/850 Series
(11)Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
ParameterPeripheral input “H” pulse width 1Peripheral input “L” pulse width 1
SymboltILIH1tIHIL1
Pin
Condition
ValueMin.2 tinst*2 tinst*
Max.——
Unitµsµs
Remarks
TRGI, DTTI,ADST,
INT0 to INT3Load condition:50 pF
* :For information on tinst, see “(4) Instruction Cycle.”
TRGIDTTIADSTINT0 to INT30.2 VCCtIHIL1tILIH10.8 VCC0.2 VCC0.8 VCC5.A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
ResolutionLinearity error
Differential linearity errorTotal error
Zero transition voltage
VOT
AVCC = VCC
AN0 to AN7—Symbol
Pin
Condition
Value
Min.————AVSS – 1.5AVR – 3.5—
————
AVR
AVR = 5.0 V
——00—
Typ.————AVSS + 0.5AVR – 1.5—33 tinst*———200
Max.10±2.0±1.5±3.0AVSS + 2.5AVR + 0.54—10AVRAVCC—
UnitRemarksbitLSBLSBLSBLSBLSBLSBµsµAVVµA
Full-scale transition voltageVFSTInterchannel disparityA/D mode conversion timeAnalog port input currentAnalog input voltageReference voltageReference voltage supply current
IRIAIN
——
—AN0 to AN7
* :For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
35
MB89860/850 Series
(1)A/D Glossary
•Resolution
Analog changes that are identifiable with the A/D converter
•Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) withthe full-scale transition point (“11 1111 1111” ↔´“11 1111 1110”) from actual conversion characteristics•Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value•Total error
The total error indicates the difference between the actual value and theoretical value. This error is caused bythe zero transition error, full-scale transition error, linearity error, quantization, and noise.
Theoretical I/O value3FF3FE3FDDigital output1.5 LSBDigital outputVFST3FF3FE3FDTotal errorActual conversion value(1 LSB × N + 0.5 LSB)0040030020010.5 LSBAVSSAnalog inputAVRVOT1 LSB004VNT003002001AVSSAnalog inputAVRActual conversion valueTheoretical value1 LSB =VFST – VOT1022(V)Total error of digital output “N” =VNT – (1 LSB × N + 0.5 LSB)1 LSB(Continued)36
MB89860/850 Series
(Continued)Zero transition error004Actual conversion value003Digital outputDigital output3FE3FFFull-scale transition errorTheoretical valueActual conversion value002Actual conversion value001VFST (Measured value) 3FDActual conversion value3FC VOT (Measured value)AVSSAnalog inputAnalog inputAVRLinearity error3FF3FE3FDDigital outputDigital outputVFST(Measured value)NActual conversion value(1 LSB × N + VOT)N+1Differential linearity errorTheoretical valueActual conversion valueV(N + 1)TVNT004003002Actual conversion valueTheoretical valueN – 1VNTActual conversion value001VOT (Measured value)AVSSAnalog inputAVRN – 2Analog inputLinearity error of digital output “N” =VNT – (1 LSB × N + VOT)1 LSBDifferential linearity error of digital output “N” =V(N + 1)T – VNT1 LSB– 137
MB89860/850 Series
(2)Precautions
•Input impedance of the analog input pins
The A/D converter used for the MB89860/850 series contains a sample hold circuit as illustrated below tofetch analog input voltage into the sample hold capacitor for fifteen instruction cycles after activation A/Dconversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltagemight not stabilize within the analog input sampling period. Therefore, it is recommended to keep the outputimpedance of the external circuit low (below 10 kΩ).
Note that if the impedance connot be kept low, it is recommended to connect an external capacitor of about0.1 µF for the analog input pin.Analog Input Equivalent CircuitSample hold circuit.C = 64 pF.Anlog input pinIf the analog input impedance is higher than 10 kΩ, it isrecommended to connect an external capacitor of approx. 0.1 µF. Comparator.R = 3 kΩ.Close for 15 instruction cyclesafter activating A/D conversion.Analog channel selector•Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
38
MB89860/850 Series
sEXAMPLE CHARACTERISTICS
(1)“L” Level Output Voltage (P00 to P07, P10 to
P17, P20 to P27, P30 to P37, P50 to P57, P70 toP76, and P80 to P87)
VOL vs. IOLVOL (V)TA = +25˚C0.5VCC = 3.0 V0.40.30.20.1012345678910IOL (mA)VCC = 4.0 VVCC = 5.0 VVCC = 6.0 VVOL (mV)600500400VCC = 4.0 V300200100001234567891011121314151617181920IOL (mA)VCC = 5.0 VVCC = 6.0 V(2)“L” Level Output Voltage (P40 to P47)
VOL vs. IOLTA = +25˚CVCC = 3.0 V(3)“H” Level Output Voltage (P00 to P07, P10 to
P17, P20 to P27, P30 to P37, and P40 to P47)
(4)Pull-up Resistance
VCC − VOH vs. IOHVCC − VOH (V)1.00.90.80.70.60.50.40.30.20.10.00.0−0.5−1.0−1.5−2.0−2.5−3.0IOH (mA)VCC = 3.0 VVCC = 4.0 VVCC = 5.0 VVCC = 6.0 VTA = +25˚CRPULL vs. VCCRPULL (kΩ)1000TA = +25˚C10010 to 1123456VCC (V)39
MB89860/850 Series
(5)“H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
(6)“H” Level Input Voltage/“L” level Input
Voltage (Hysteresis Input)
VIN vs. VCCVIN (V)5.04.54.03.53.02.52.01.51.00.501234567VCC (V)TA = +25˚CVIN (V)5.04.54.03.53.02.52.01.51.00.50123VIN vs. VCCTA = +25˚CVIHSVILS4567VCC (V)VIHS:Threshold when input voltage in hysteresischaracteristics is set to “H” levelVILS:Threshold when input voltage in hysteresischaracteristics is set to “L” level(7)Operating Supply Current vs. Frequency(8)Operating Supply Current vs. VCC
ICC vs. FCICC (mA)25TA = +25˚C2020ICC (mA)25ICC vs. VCCTA = +25˚CFC = 10 MHzFC = 8 MHzFC = 6 MHzFC = 4 MHz15VCC = 5.0 V1510VCC = 3.5 V105VCC = 3.0 V50246810FC (MHz)03.03.54.04.55.05.56.0VCC (V)40
(9)Sleep Power Supply Current vs. FrequencyICCS vs. FCICCS (mA)10TA = +25˚C86VCC = 5.0 V4VCC = 3.5 V2VCC = 3.0 V0246810FC (MHz)MB89860/850 Series
(10)Sleep Power Supply Current vs. VCC
ICCS vs. VCCICCS (mA)10TA = +25˚C8FC = 10 MHz6FC = 8 MHzFC = 6 MHz4FC = 4 MHz203.03.54.04.55.05.56.0VCC (V)41
MB89860/850 Series
sINSTRUCTIONS
Execution instructions can be divided into the following four groups: ••••
Transfer
Arithmetic operation Branch Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symboldiroffext#vct#d8#d16dir: brel@AAHALTTHTLIX
Direct address (8 bits)Offset (8 bits)
Extended address (16 bits)Vector table number (3 bits)Immediate data (8 bits)Immediate data (16 bits)Bit direct address (8:3 bits) Branch relative address (8 bits)
Register indirect (Example: @A, @IX, @EP)
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)Upper 8 bits of accumulator A (8 bits)Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of temporary accumulator T (8 bits)Lower 8 bits of temporary accumulator T (8 bits)Index register IX (16 bits)
Meaning
(Continued)42
MB89860/850 Series
(Continued) SymbolEPPCSPPSdrCCRRPRi×( × )(( × ))
Extra pointer EP (16 bits)Program counter PC (16 bits)Stack pointer SP (16 bits)Program status PS (16 bits)
Accumulator A or index register IX (16 bits)Condition code register CCR (8 bits)Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Meaning
Columns indicate the following: Mnemonic:~:#:Operation:TL, TH, AH:
Assembler notation of an instruction Number of instructions Number of bytes
Operation of an instruction
A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following:
•“–” indicates no change.
•dH is the 8 upper bits of operation description data.
•AL and AH must become the contents of AL and AH immediately before the instruction is executed. •00 becomes 00.
N, Z, V, C:OP code:
An instruction of which the corresponding flag will change. If + is written in this column,the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
43
MB89860/850 Series
Table 2 Transfer Instructions (48 instructions)
MnemonicMOV dir,A
MOV @IX +off,AMOV ext,AMOV @EP,AMOV Ri,AMOV A,#d8MOV A,dir
MOV A,@IX +offMOV A,extMOV A,@AMOV A,@EPMOV A,RiMOV dir,#d8
MOV @IX +off,#d8MOV @EP,#d8MOV Ri,#d8MOVW dir,A
MOVW @IX +off,AMOVW ext,AMOVW @EP,AMOVW EP,AMOVW A,#d16MOVW A,dir
MOVW A,@IX +offMOVW A,extMOVW A,@AMOVW A,@EPMOVW A,EPMOVW EP,#d16MOVW IX,AMOVW A,IXMOVW SP,AMOVW A,SPMOV @A,TMOVW @A,TMOVW IX,#d16MOVW A,PSMOVW PS,AMOVW SP,#d16SWAP
SETB dir: bCLRB dir: bXCH A,TXCHW A,TXCHW A,EPXCHW A,IXXCHW A,SPMOVW A,PC
~344332344333454445542345544232222343223244233332
#223112223111332222311322311131111113113122111111
Operation
(dir) ← (A)
( (IX) +off ) ← (A)(ext) ← (A)( (EP) ) ← (A)(Ri) ← (A)(A) ← d8(A) ← (dir)
(A) ← ( (IX) +off)(A) ← (ext)(A) ← ( (A) )(A) ← ( (EP) )(A) ← (Ri)(dir) ← d8
( (IX) +off ) ← d8( (EP) ) ← d8(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)( (IX) +off) ← (AH),( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)( (EP) ) ← (AH),( (EP) + 1) ← (AL)(EP) ← (A)(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)(AH) ← ( (IX) +off),(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)(A) ← (EP)(EP) ← d16(IX) ← (A)(A) ← (IX)(SP) ← (A)(A) ← (SP)( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)(IX) ← d16(A) ← (PS)(PS) ← (A)(SP) ← d16(AH) ↔ (AL)(dir): b ← 1(dir): b ← 0(AL) ↔ (TL)(A) ↔ (T)(A) ↔ (EP)(A) ↔ (IX)(A) ↔ (SP)(A) ← (PC)
TL–––––ALALALALALALAL–––––––––ALALALALALAL–––––––––––––––ALAL––––
TH–––––––––––––––––––––AHAHAHAHAHAH––––––––––––––––AH––––
AH–––––––––––––––––––––dHdHdHdHdHdHdH––dH–dH–––dH––AL–––dHdHdHdHdH
N Z V C– – – –– – – –– – – –– – – –– – – –+ + – –+ + – –+ + – –+ + – –+ + – –+ + – –+ + – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –+ + – –+ + – –+ + – –+ + – –+ + – –+ + – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –+ + + +– – – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –
OP code4546614748 to 4F
04050660920708 to 0F
85868788 to 8F
D5D6
D4D7E3E4C5C6C493C7F3E7E2F2E1F18283E67071E510A8 to AFA0 to A7
4243F7F6F5F0
Notes:•During byte transfer to A, T ← A is restricted to low bytes.
•Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
44
MB89860/850 Series
Table 3 Arithmetic Operation Instructions (62 instructions)
MnemonicADDC A,RiADDC A,#d8ADDC A,dir
ADDC A,@IX +offADDC A,@EPADDCW AADDC ASUBC A,RiSUBC A,#d8SUBC A,dir
SUBC A,@IX +offSUBC A,@EPSUBCW ASUBC AINC RiINCW EPINCW IXINCW ADEC RiDECW EPDECW IXDECW AMULU ADIVU AANDW AORW AXORW ACMP ACMPW ARORC AROLC ACMP A,#d8CMP A,dirCMP A,@EPCMP A,@IX +offCMP A,RiDAADASXOR AXOR A,#d8XOR A,dirXOR A,@EPXOR A,@IX +offXOR A,RiAND AAND A,#d8AND A,dir
~3234332323433243334333192133323222334322223343223
#12221111222111111111111111111112212111122121122
Operation
(A) ← (A) + (Ri) + C(A) ← (A) + d8 + C(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C(A) ← (A) + ( (EP) ) + C(A) ← (A) + (T) + C(AL) ← (AL) + (TL) + C(A) ← (A) − (Ri) − C(A) ← (A) − d8 − C(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C(A) ← (A) − ( (EP) ) − C(A) ← (T) − (A) − C(AL) ← (TL) − (AL) − C(Ri) ← (Ri) + 1(EP) ← (EP) + 1(IX) ← (IX) + 1(A) ← (A) + 1(Ri) ← (Ri) − 1(EP) ← (EP) − 1(IX) ← (IX) − 1(A) ← (A) − 1(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)(A) ← (A) ∧ (T)(A) ← (A) ∨ (T)(A) ← (A) ∀ (T)
(TL) − (AL)(T) − (A) →A→C
←A ←C
TL–
––––––––––––––––––––––dL–––––––––––––––––––––––
TH–––––––––––––––––––––––00–––––––––––––––––––––––
AH–––––dH––––––dH––––dH–––dHdH00dHdHdH––––––––––––––––––––
N Z V C+ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + –– – – –– – – –+ + – –+ + + –– – – –– – – –+ + – –– – – –– – – –+ + R –+ + R –+ + R –+ + + ++ + + ++ + – ++ + – ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + + ++ + R –+ + R –+ + R –+ + R –+ + R –+ + R –+ + R –+ + R –+ + R –
OP code28 to 2F
24252627232238 to 3F
343536373332C8 to CF
C3C2C0D8 toDF
D3D2D00111637353121303
021415171618 to 1F
8494525455575658 to 5F
626465
(A) − d8(A) − (dir)(A) − ( (EP) )(A) − ( (IX) +off)(A) − (Ri)
Decimal adjust for additionDecimal adjust for subtraction(A) ← (AL) ∀ (TL)(A) ← (AL) ∀ d8(A) ← (AL) ∀ (dir)(A) ← (AL) ∀ ( (EP) )(A) ← (AL) ∀ ( (IX) +off)(A) ← (AL) ∀ (Ri)(A) ← (AL) ∧ (TL)(A) ← (AL) ∧ d8(A) ← (AL) ∧ (dir)
(Continued)45
MB89860/850 Series
(Continued) MnemonicAND A,@EPAND A,@IX +offAND A,RiOR AOR A,#d8OR A,dirOR A,@EPOR A,@IX +offOR A,RiCMP dir,#d8CMP @EP,#d8CMP @IX +off,#d8CMP Ri,#d8INCW SPDECW SP
~343223343545433
#121122121323211
Operation
(A) ← (AL) ∧ ( (EP) )(A) ← (AL) ∧ ( (IX) +off)(A) ← (AL) ∧ (Ri)(A) ← (AL) ∨ (TL)(A) ← (AL) ∨ d8(A) ← (AL) ∨ (dir)(A) ← (AL) ∨ ( (EP) )(A) ← (AL) ∨ ( (IX) +off)(A) ← (AL) ∨ (Ri)
(dir) – d8( (EP) ) – d8( (IX) +off) – d8(Ri) – d8(SP) ← (SP) + 1(SP) ← (SP) – 1
TL–––––––––––––––
TH–––––––––––––––
AH–––––––––––––––
N Z V C+ + R –+ + R –+ + R –+ + R –+ + R –+ + R –+ + R –+ + R –+ + R –+ + + ++ + + ++ + + ++ + + +– – – –– – – –
OP code676668 to 6F
727475777678 to 7F
95979698 to 9F
C1D1
Table 4 Branch Instructions (17 instructions)
MnemonicBZ/BEQ relBNZ/BNE relBC/BLO relBNC/BHS relBN relBP relBLT relBGE rel
BBC dir: b,relBBS dir: b,relJMP @AJMP extCALLV #vctCALL extXCHW A,PCRET RETI
~33333333552366346
#22222222331313111
Operation
If Z = 1 then PC ← PC + relIf Z = 0 then PC ← PC + relIf C = 1 then PC ← PC + relIf C = 0 then PC ← PC + relIf N = 1 then PC ← PC + relIf N = 0 then PC ← PC + relIf V ∀ N = 1 then PC ← PC + relIf V ∀ N = 0 then PC ← PC + reIIf (dir: b) = 0 then PC ← PC + relIf (dir: b) = 1 then PC ← PC + rel(PC) ← (A)(PC) ← extVector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1Return from subrountineReturn form interrupt
TL–––––––––––––––––
TH–––––––––––––––––
AH––––––––––––––dH––
N Z V C– – – –– – – –– – – –– – – –– – – –– – – –– – – –– – – –– + – –– + – –– – – –– – – –– – – –– – – –– – – –– – – –Restore
OP codeFDFCF9F8FBFAFFFEB0 to B7B8 to BF
E021E8 to EF
31F42030
Table 5 Other Instructions (9 instructions)
MnemonicPUSHW APOPW APUSHW IXPOPW IXNOPCLRCSETCCLRISETI
~444411111
#111111111
Operation
TL–––––––––
TH–––––––––
AH–dH–––––––
N Z V C– – – –– – – –– – – –– – – –– – – –– – – R– – – S– – – –– – – –
OP code
405041510081918090
46
3RETISETCCLRBBBCINCWDECWMOVWMOVWdir: 1 dir: 1,relSPSPSP,AA,SPPUSHWPOPWMOVMOVWCLRIAAA,extA,PSLSETICLRBBBC INCWDECWJMPMOVWdir: 0 dir: 0,relAA@AA,PCH456789ABCDEF0120NOPSWAPRET1SUBCMULUDIVUAXCHXORANDORAA, TAAPUSHWPOPWMOVMOVWCLRCJMPCALLIXIXext,APS,AAaddr16addr162ROLCCMPADDCAAAMOVMOVCLRBBBC INCWDECWMOVWMOVWA@A,TA,@Adir: 2 dir: 2,relIXIXIX,AA,IXsINSTRUCTION MAP
3XORANDORDAAA,#d8A,#d8A,#d8DASRORCMOVWMOVWCLRBBBC INCWDECWMOVWMOVWCMPWADDCWSUBCWXCHWXORWANDWORWAAA, TAAA@A,TA,@Adir: 3 dir: 3,relEPEPEP,AA,EPAACLRBBBC MOVWMOVWMOVWXCHWdir: 4dir: 4,relA,extext,AA,#d16A,PC4MOVCMPADDCSUBCA,#d8A,#d8A,#d8A,#d85SUBC A,@IX +d@IX +d,#d8@IX +d,#d8MOVCMPADDCSUBCMOVXORANDORMOVCMPCLRBBBC MOVWMOVWMOVWXCHWA,dirA,dirA,dirA,dirdir,AA,dirA,dirA,dirdir,#d8dir,#d8dir: 5dir: 5,relA,dirdir,ASP,#d16A,SPMOV @IX XOR AND +d,AA,@IX +dA,@IX +dMOV @EP,#d8CMP@EP,#d8OR A,@IX +d6MOV A,@IX +dCMP A,@IX +dADDC A,@IX +dMOVCMPCLRBBBC dir: 6dir: 6,relMOVW MOVW A,@IX +d@IX +d,AMOVWXCHWIX,#d16A,IX7MOV CMP ADDC SUBC MOV XOR AND OR A,@EPA,@EPA,@EPA,@EP@EP,AA,@EPA,@EPA,@EPCLRBBBC MOVW MOVW MOVWXCHWdir: 7dir: 7,relA,@EP@EP,AEP,#d16A,EP8MOVCMPADDCSUBCMOVXORANDORMOVCMPSETBBBS INCDECCALLVBNCA,R0A,R0A,R0A,R0R0,AA,R0A,R0A,R0R0,#d8R0,#d8dir: 0dir: 0,rel R0R0 #0 relrelrelrel9MOVCMPADDCSUBCMOVXORANDORMOVCMPSETBBBS INCDECCALLVBCA,R1A,R1A,R1A,R1R1,AA,R1A,R1A,R1R1,#d8R1,#d8dir: 1dir: 1,relR1R1#1AMOVCMPADDCSUBCMOVXORANDORMOVCMPSETBBBS INCDECCALLVBPA,R2A,R2A,R2A,R2R2,AA,R2A,R2A,R2R2,#d8R2,#d8dir: 2dir: 2,relR2R2#2BMOVCMPADDCSUBCMOVXORANDORMOVCMPSETBBBS INCDECCALLVBNA,R3A,R3A,R3A,R3R3,AA,R3A,R3A,R3R3,#d8R3,#d8dir: 3dir: 3,relR3R3#3CMOVCMPADDCSUBCMOVXORANDORMOVCMPSETBBBS INCDECCALLVBNZA,R4A,R4A,R4A,R4R4,AA,R4A,R4A,R4R4,#d8R4,#d8dir: 4dir: 4,relR4R4 #4relrelDMOVCMPADDCSUBCMOVXORANDORMOVCMPSETBBBS INCDECCALLVBZA,R5A,R5A,R5A,R5R5,AA,R5A,R5A,R5R5,#d8R5,#d8dir: 5dir: 5,relR5R5#5EMOVCMPADDCSUBCMOVXORANDORMOVCMPSETBBBS INCDECCALLVBGEA,R6A,R6A,R6A,R6R6,AA,R6A,R6A,R6R6,#d8R6,#d8dir: 6dir: 6,rel R6 R6 #6relMB89860/850 Series
FMOVCMPADDCSUBCMOVXORANDORMOVCMPSETBBBS INCDECCALLVBLTA,R7A,R7A,R7A,R7R7,AA,R7A,R7A,R7R7,#d8R7,#d8dir: 7dir: 7,relR7 R7 #7rel47
MB89860/850 Series
sMASK OPTIONS (MB89855/857/865/867)
Option type
Power-on reset
Initial value of oscillation stabilization delay timeReset pin output
Pull-up resistor at port pin
P00 to P07, P10 to P17,P20 to P27, P30 to P37,P40 to P47, P60 to P64,P70 to P76, P80 to P87
Option selection
0: Without power-on reset1: With power-on reset0: 218/FC (s) (Crystal oscillator)1: 214/FC (s) (Ceramic oscillator)0: Without reset output1: With reset output
Remarks
—
Selects the initial value of the OSCS bit in the STBC register during power-on reset.
—
•Can be set per pin.
•P70 to P76, and P80 to P87 are used in the MB89860 series only.
•P00 to P07, P10 to P17, and P20 to P27 with a pull-up resistor can be set only for single-chip mode.
1: Without pull-up resistor0: With pull-up resistor
sSTANDARD OPTION LIST
Part number
ParameterPower-on reset
Initial value of oscillation stabilization delay timeOutput at reset pinPull-up resistor at port pin
MB89P857/W857/P867/W867/T855
Available218/FC (s)AvailableNot available
sORDERING INFORMATION
Part number
MB89865PFMB89867PFMB89P867PFMB89855P-SHMB89T855P-SHMB89857P-SHMB89P857P-SHMB89W867CFMB89W857C-SH
Package80-pin Plastic QFP(FPT-80P-M06)64-pin Plastic SH-DIP(DIP-64P-M01)80-pin Ceramic QFP(FPT-80C-A02)64-pin Ceramic SH-DIP
(DIP-64C-A06)
ES level onlyES level onlyRemarks
48
MB89860/850 Series
sPACKAGE DIMENSIONS80-pin Plastic QFP(FPT-80P-M06)23.90±0.40(.941±.016)646520.00±0.20(.787±.008)41403.35(.132)MAX0.05(.002)MIN(STAND OFF)14.00±0.20(.551±.008)INDEX802517.90±0.40(.705±.016)12.00(.472)REF16.30±0.40(.642±.016)\"A\"LEAD No.1240.80(.0315)TYP0.35±0.10(.014±.004)0.16(.006)M0.15±0.05(.006±.002)Details of \"A\" part0.25(.010)\"B\"0.10(.004)18.40(.724)REF22.30±0.40(.878±.016)0.30(.012)0.18(.007)MAX0.58(.023)MAXDetails of \"B\" part0 10°0.80±0.20(.031±.008)1994 FUJITSU LIMITED F80010S-3C-2Dimensions in mm (inches)64-pin Plastic SH-DIP(DIP-64P-M01)58.00–0.55+.0082.283–.022+0.22INDEX-1INDEX-217.00±0.25(.669±.010)5.65(.222)MAX3.00(.118)MIN1.00–0+.020.039–01.778±0.18(.070±.007)1.778(.070)MAX55.118(2.170)REF+0.500.25±0.05(.010±.002)0.45±0.10(.018±.004)0.51(.020)MIN15°MAX19.05(.750)TYPC1994 FUJITSU LIMITED D64001S-3C-4Dimensions in mm (inches)49MB89860/850 Series
80-pin Ceramic QFP(FPT-80P-A02)0.51(.020) TYP8.50(.335)TYP12.00(.472)REF17.91(.705)TYP16.00(.630)14.00±0.25TYP(.551±.010)16.31(.642)TYPINDEX AREA0.80±0.100.35–0.07(.0315±.0040)(.014±.003)18.40(.725) REF20.00±0.25(.787±.010)23.90(.941) TYP22.00(.866) TYP+0.080.80±0.10(.0315±.0040)0.15±0.05(.006±.002)1.60(.063) TYP4.45(.175)MAX22.30(.878) TYP0.80(.0315) TYPC1994 FUJITSU LIMITED F80014SC-1-2Dimensions in mm (inches)64-pin Ceramic SH-DIP(DIP-64C-A06)56.90±0.56(2.240±.022)R1.27(.050)REF8.89(.350) DIATYP18.75±0.25(.738±.010)INDEX AREA5.84(.230)MAX1.27±0.25(.050±.010)0.25±0.05(.010±.004)3.40±0.36(.134±.014)1.778±0.180(.070±.007)0.90±0.10(.0355±.0040)55.118(2.170)REF0.46–0.08+.005.018–.003+0.1319.05±0.25(.750±.010)0°~9°1.45(.057)MAXC1994 FUJITSU LIMITED D64006SC-1-2Dimensions in mm (inches)50FUJITSU LIMITED
For further information please contact:Japan
FUJITSU LIMITED
Corporate Global Business Support DivisionElectronic Devices
KAWASAKI PLANT, 1015, KamikodanakaNakahara-ku, Kawasaki-shiKanagawa 211, JapanTel: (044) 754-3753Fax: (044) 754-3329
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F9606
© FUJITSU LIMITED Printed in Japan
MB89860/850 Series
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as ameans of illustrating typical semiconductor applications. Com-plete information sufficient for construction purposes is not nec-essarily given.
The information contained in this document has been carefullychecked and is believed to be reliable. However, Fujitsu as-sumes no responsibility for inaccuracies.
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51
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