元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004featuresapplicationDSingle-Chip CCD Analog Front-EndD10-Bit, 40-MSPS†, A/D-Converter Single 3-VDDDDDDSupply OperationVery Low Power: 200 mW Typical, 2-mWPower-Down ModeDifferential Nonlinearity Error: < ±0.6 LSB TypicalIntegral Nonlinearity Error: <±1.75 LSBTypicalProgrammable Gain Amplifier (PGA) With0-dB to 36-dB Gain Range (0.045 dB/Step)Automatic or Programmable Optical BlackLevel and Offset Calibration With DigitalFilter and Bad Pixel LimitsAdditional DACs for External AnalogSettingSerial Interface for Register ConfigurationInternal-Reference VoltagesDDigital Still CameraDVideo CamcorderPFB PACKAGE(TOP VIEW)363534333231302928272625STBYRESETCSSDINSCLKADCCLKBLKGCPCPAVDD4AGND4OBCLP DDD48-Pin TQFP PackageAGND5RBDRMDRPDAVDD5VSSAVDD1AGND1SRSVCLCCDCLREF373839404142434445464748123456789101112TLV990-40PFB242322212019181716151413OESCKPDACO2DACO1AGND3AVDD3DIGNDDIVDDD9D8D7D6The TLV990-40 is a complete CCD and videosignal processor/digitizer designed for digital stillcamera and video camcorder applications.The TLV990-40 performs all the analog-processing functions necessary to maximize the dynamic range,corrects various errors associated with the CCD sensor, and then digitizes the results with an on-chiphigh-speed analog-to-digital converter (ADC).The key components of the TLV990-40 include: an input clamp circuit for CCD and analog video signals, acorrelated double sampler (CDS), a programmable-gain amplifier (PGA) with 0 to 36-dB gain range, two internaldigital-to-analog converters (DAC) for automatic or programmable optical black level and offset calibration, a10-bit, 40-MSPS pipeline ADC, a parallel data port for easy microprocessor interface, a serial port forconfiguring internal control registers, two additional DACs for external system control, and internal referencevoltages.Designed in advanced CMOS process, the TLV990-40 operates from a single 3-V power supply with a normalpower consumption of 200 mW at 40 MSPS, and 2 mW in power-down mode.Its very high throughput rate, single 3-V operation, very low-power consumption, and fully-integrated analogprocessing circuitry make the TLV990-40 an ideal CCD and video signal-processing solution for electronicvideo-camcorder applications.This device is available in a 48-pin TQFP package and is specified over a –20°C to 75°C operating-temperaturerange.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.†The test register must be set to 1011 for 40 MSPS operation.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•CCDINNCAVDD2AGND2DGNDDVDDD0D1D2D3D4D5descriptionCopyright 2004, Texas Instruments Incorporated1元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDAVAILABLE OPTIONSPACKAGE DEVICETA−20°C to 75°CTQFP(PFB)TLV990-40PFBSLAS326A − JANUARY 2001 − REVISED MARCH 2004functional block diagramAVDD1−5CLCCDCLREFRPDRBDRMDDVDDDIVDDOEThreeStateLatchD0D9RESETCLKSVSRBLKGOBCLPSTBYINT. REF.Clamp1.2 V REFCDS/MUXCCDINΣ8-BitCDACPGA10PGARegulatorΣ8-BitFDAC10-BitADCOpticalBlackPixel LimitsOffsetRegisterOffsetRegisterDigitalAverager/FilterTimingandControlLogicDACO18-BitDACDACREGSCKPCSSCLKSDINDACO28-BitDACDACREGSerialPortVSSAGND1−5DGNDDIGND2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004Terminal FunctionsTERMINALNAMEADCCLKAGND1AGND2AGND3AGND4AGND5AVDD1AVDD2AVDD3AVDD4AVDD5BLKGCLCCDCCDINCLREFCPCSD0 – D9DACO1DACO2DGNDDIGNDDIVDDDVDDNCOBCLPOERBDRESETRMDRPDSDINSCKPSCLKSRSTBYSVVSSNO.25444203237433193341364714834, 35287–162122518176231243829394027232645304642IIIOIOOIIIIIIIIIOIIOOOIADC clock inputAnalog ground for internal CDS circuitsAnalog ground for internal PGA circuitsAnalog ground for internal DAC circuitsAnalog ground for internal ADC circuitsAnalog ground for internal REF circuitsAnalog supply voltage for internal CDS circuits, 3 VAnalog supply voltage for internal PGA circuits, 3 VAnalog supply voltage for internal DAC circuits, 3 VAnalog supply voltage for internal ADC circuits, 3 VAnalog supply voltage for internal ADC circuits, 3 VControl input. The CDS operation is disabled when BLKG is pulled low.CCD signal clamp control inputCCD inputClamp reference voltage outputConnect this pin to AVDD.Chip select. A logic low on this input enables the serial port.10-bit 3-state ADC output data or offset DACs test dataDigital-to-analog converter output1Digital-to-analog converter output2Digital groundDigital interface circuit groundDigital interface circuit supply voltage, 1.8 V− 4.4 VDigital supply voltage, 3 VNot connectedOptical black level and offset calibration control input. Active low.Output data enable. Active low.Internal bandgap reference for external decouplingHardware-reset input, active low. This signal forces a reset of all internal registersRef− output for external decouplingRef+ output for external decouplingSerial data input to configure the internal registersSelects the polarity of SCLK. 0 – active low (high when SCLK is not running), 1 – active high (low whenSCLK is not running)Serial clock input. This clock synchronizes the serial data transfer.CCD reference level sample clock inputHardware power-down control input, active lowCCD signal level sample clock inputSilicon substrate, normally connected to analog groundI/ODESCRIPTIONPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDabsolute maximum ratings over operating free-air temperature (unless otherwise noted)†Supply voltage, AVDD, DVDD, DIVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 VAnalog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD+0.3 VDigital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD+0.3 VOperating virtual junction temperature range, TJ −40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°COperating free-air temperature range, TA −20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 75°CStorage temperature range, Tstg −65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.SLAS326A − JANUARY 2001 − REVISED MARCH 2004recommended operating conditionspower suppliesMINAnalog supply voltageDigital supply voltageDigital interface supply voltageAVDDDVDDDIVDD2.72.71.8NOM33MAX3.33.34.4UNITVVVdigital inputs, DIVDD = 3 V, DVDD = 3 VMINHigh-level input voltage, VIHLow-level input voltage, VILInput ADCCLK frequencyADCCLK pulse duration, clock high, tw(MCLKH)ADCCLK pulse duration, clock low, tw(MCLKL)Input SCLK frequencySCLK pulse duration, clock high, tw(SCLKH)SCLK pulse duration, clock low, tw(SCLKL)12.512.512.512.5400.8DIVDD0.2DIVDD40NOMMAXUNITVVMHznsnsMHznsns4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004electrical characteristics over recommended operating free-air temperature range, TA = 25°C,AVDD=DVDD=3 V, ADCCLK=40 MHz (unless otherwise noted)total devicePARAMETERAVDD operating currentDVDD operating currentDevice power consumptionPower consumption in power-down modeINLDNLFull channel integral nonlinearityFull channel differential nonlinearityNo missing codeFull channel output latencyAVDD=DVDD= 2.7 V – 3.3 V,Using best fit methodAVDD=DVDD= 2.7 V – 3.3 V,ADCCLK=18 MSPS, 10 bitsTEST CONDITIONSMINTYP5682002±1.75±0.5Assured6CLKcycles±2.15±0.99MAXUNITmAmAmWmWLSBLSBanalog-to-digital converter (ADC)PARAMETERADC resolution in CCD modeFull scale input spanConversion rateTEST CONDITIONSMINTYP10240MAXUNITBitsVP-PMHzcorrelated double sample (CDS) and programmable gain amplifier (PGA)PARAMETERCDS and PGA sample rateCDS full-scale input spanInput capacitance of CDSMinimum PGA gainMaximum PGA gainPGA gain resolutionPGA programming code resolution35Single-ended input40360.04510137TEST CONDITIONSMINTYPMAX401UNITMHzVpFdBdBdBBitsinternal digital-to-analog converters (DAC) for offset correctionPARAMETERDAC resolutionINLDNLIntegral nonlinearityDifferential nonlinearityOutput settling timeTo 1% accuracyTEST CONDITIONSMINTYP8±0.5±0.580MAXUNITBitsLSBLSBnsPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDelectrical characteristics over recommended operating free-air temperature range, TA = 25°C,AVDD=DVDD=3 V, ADCCLK=40 MHz (unless otherwise noted)user digital-to-analog converters (DAC)PARAMETERDAC resolutionINLDNLIntegral nonlinearityDifferential nonlinearityOutput voltage rangeOutput settling time10 pF external load, settle to 1 mV04TEST CONDITIONSMINTYP8±0.75±0.5VDDMAXUNITBitsLSBLSBVµsSLAS326A − JANUARY 2001 − REVISED MARCH 2004reference voltagesPARAMETERInternal bandgap voltage referenceTemperature coefficientADC Ref+ADC Ref−Externally decoupledTEST CONDITIONSMIN1.43TYP1.5010021MAX1.58UNITVppm/°CVVdigital specificationsPARAMETERLogic inputsIIHIILCiVOHVOLIOZCoHigh-level input currentLow-level input currentInput capacitanceHigh-level output voltageLow-level output voltageHigh-impedance-state output currentOutput capacitanceIOH = 50 µA, DIVDD = 3 VIOL = 50 µA, DIVDD = 3 VDIVDD = 3 V−10−105DIVDD−0.40.4±1051010µApFVVµApFTEST CONDITIONSMINTYPMAXUNITLogic outputskey timing requirementsPARAMETERtSRWtSVWtODtCSFtCSRSR pulse widthSV pulse widthADCCLK-to-output data delayCS falling edge to SCLK rising edgeSCLK falling edge to CS rising edge05TEST CONDITIONSMeasured at 50% of pulse heightMIN10106TYPMAXUNITnsnsnsnsns6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 200410 BIT-PGA GAIN CURVE40353025201510500200400600800PGA Codes10001200Gain − dBFigure 1TYPICAL CHARACTERISTICSOptical Black IntervalCCDOutputnn+1Dummy Black(Blanking) IntervalSignal IntervalSRtSRWSVtSvWBLKGCLCCDOBCLPADCCLKtODADC OUTLatency: 6 ADC CyclesnFigure 2. System Operation Timing DiagramPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•7元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDTYPICAL CHARACTERISTICStCSFCS1SCLK23456716tCSRSLAS326A − JANUARY 2001 − REVISED MARCH 2004SDINDI15DI14DI13DI12DI11DI10DI9DI0SCKP Pin Is Pulled LowtCSFCS1SCLK234567tCSR16SDINDI15DI14DI13DI12DI11DI10DI9DI0SCKP Pin Is Pulled HighFigure 3. Serial Interface Timing Diagram8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004TYPICAL CHARACTERISTICStSRDCCD INtSVDSRSVtADC_SVADCCLKTIMING PARAMETERtSRDDelay between sample reset (SR) rising edge andactual sampling instant (ns)Delay between sample video (SV) rising edge andactual instant of video signal sampling (ns)Time between ADCCLK falling edge and SV fallingedgeMIN6TYPMAXEXPLANATIONThis is the fixed internal delay in the chip. The resetvalue of the CCD waveform should be stable untilthe end of this period.This is the fixed internal delay in the chip. The videosignal value of the CCD waveform should be stableuntil the end of this period.The timing margin required to ensure the ADCCLKpositive half cycle is in between two SV pulsestSVD6tADC_SV3Figure 4. Detailed Internal Timing DiagramPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•9元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDAPPLICATION INFORMATIONAVDD0.1 µF1 µFAVDD0.1 µF0.1 µF0.1 µFInputs1 µF1 µF1 µFSLAS326A − JANUARY 2001 − REVISED MARCH 2004CLCCDCLREFSRAGND1RBDAGND5AVDD1VSSAVDD5RPDRMDSVAreaCCD0.1 µF1 µF484746454443424140393837AVDD0.1 µFBLKGCPCP36353433Input12AVDD0.1 µFDVDD0.1 µF3456789101112CCDINNCAVDD2AGND2DGNDDVDDD0D1D2D3D4D5D9DIVDDD6D7D8TLV990-40PFBAGND3DACO1DACO2DIGNDAVDD3AVDD432AGND431OBCLP30STBY29RESET28CS27SDIN26SCLK25ADCCLKSCKPOEInputs131415161718192021222324InputsD (0−9)AVDD − 3 VDVDD − 3 VDIVDD − 1.8 V to 4.4 VDIVDD0.1 µFAVDD0.1 µFAnalog GNDDigital GNDNOTE:All analog outputs should be buffered if the load is resistive, or if the load is capacitive and greater than 2 pF.Figure 5. Typical Application Connection10POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004REGISTER DEFINITIONserial input data formatDI15XA3000000001111111A2000011110000111DI14XA1001100110011001DI13A3A0010101010101010Control register1PGA gain registerUser DAC1 registerUser DAC2 registerCoarse offset DACFine offset DACDigital Vb register (sets reference code level at the ADC output during the optical black interval)Optical black setup register (sets the number of black pixels per line for digital averaging)Hot/cold pixel limit register (sets the limit for maximum positive deviation of optical black pixel from Vb value)ReservedControl register2 (sets the weight for digital filtering and video modes)Blanking data register (The data in this register appears at digital output during blanking (BLKG is low))ADCCLK internal programmable delay registerSR and SV internal programmable delay registerTest registerDI12A2DI11A1DI10A0DI9D9DI8D8DI7D7DI6D6DI5D5DI4D4DI3D3DI2D2DI1D1DI0D0D9−D010-bit data be to written into the selected registercontrol register1 formatD9STBYD8PDD1D7PDD2D6ACDD5AFDD4OBMD3XD2SRSVD1RTOBD0RTSYcontrol register1 descriptionBITD9D8D7D6NAMESTBYPDD1PDD2ACDDESCRIPTIONDevice power-down control: 1 = standby, 0 = active (default)Power-down user DAC1: 1 = standby, 0 = active (default)Power-down user DAC2: 1 = standby, 0 = active (default)Coarse-offset DAC mode control:0 = autocalibration (default), 1 = bypass autocalibration.Note: When D6 is set to 0, D5 must also be set to 0 (automode). Otherwise, the automode will be disabled on both offset DACs.Fine offset DAC mode control:0 = autocalibration (default), 1 = bypass autocalibration.Note: D5 can be set to 0 with or without D6 being set to 0.This bit initiates the offset DACs starting sequence.0 = coarse-offset DAC starts first (default)1 = fine-offset DAC starts firstReservedThis bit specifies the polarity of SR and SV input pulses.0 – SR/SV active low (default)1 – SR/SV active highWriting 1 to this bit will reset calculated black-level results in the digital averager.Writing 1 to this bit will reset entire system to the default settings (edge sensitive).D5AFDD4OBMD3D2XSRSVD1D0RTOBRTSYPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•11元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDREGISTER DEFINITIONPGA register formatD9Bit 9D8Bit 8D7Bit 7D6Bit 6D5Bit 5D4Bit 4D3Bit 3D2Bit 2D1Bit 1D0Bit 0SLAS326A − JANUARY 2001 − REVISED MARCH 2004Default PGA gain = 0000000000 or 0 dBuser DAC1 and DAC2 registers formatD9XD8XD7Bit 7D6Bit 6D5Bit 5D4Bit 4D3Bit 3D2Bit 2D1Bit 1D0Bit 0Default user DAC register value = XX00000000coarse offset DAC register formatD9XD8SIGND7Bit 7D6Bit 6D5Bit 5D4Bit 4D3Bit 3D2Bit 2D1Bit 1D0Bit 0coarse offset DAC register descriptionBITD9D8D7−D0NAMEXSIGNReservedCoarse DAC sign bit, 0 = + sign (default), 1 = − signCoarse DAC control data when the D6 in the control register is set at 1.DESCRIPTIONDefault coarse DAC register value = X000000000fine offset DAC register formatD9XD8SIGND7Bit 7D6Bit 6D5Bit 5D4Bit 4D3Bit 3D2Bit 2D1Bit 1D0Bit 0fine offset DAC register descriptionBITD9D8D7−D0NAMEXSIGNReservedFine DAC sign bit, 0 = + sign (default), 1 = − signFine DAC control data when the D5 in the control register is set at 1.DESCRIPTIONDefault fine DAC register value = X000000000digital Vb (optical black level) register formatD9Bit 9D8Bit 8D7Bit 7D6Bit 6D5Bit 5D4Bit 4D3Bit 3D2Bit 2D1Bit 1D0Bit 0Default Vb register value = 40 Hex12POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004REGISTER DEFINITIONoptical black setup register formatD9OMUX1D8OMUX0D7HYSD6XD5SOFW1D4SOFW0D3MPD2PN2D1PN1D0PN0optical black setup register descriptionBITD8, D9NAMEOMUX1,OMUX0DESCRIPTIONThese two bits multiplex digital output (data presented at D[9:0] pins):OMUX1OMUX000D[9:0] = ADC output (default)01D[9:0] = ADC output10D[9] = fine/coarse (1/0) autocorrection flagD[8] = coarse DAC signD[7:0] = coarse DAC value11D[9] = fine/coarse (1/0) autocorrection flagD[8] = fine DAC signD[7:0] = fine DAC valueSets the hysteresis0 − Apply hysteresis to FDAC (default)1 − No hysteresisReservedThese two bits set the digital filter weight when SOF is activated (the SOF bit in control register 2 is set to 1).SOFW1SOFW0Weight00 0 (default)01 110 211 3When this bit is 1, the number of optical black pixels to be averaged per line (2N) is multiplied by 3.By setting the MP and PN2−PN0 bits together, the number of optical black pixels can be programmed to have the follow-ing numbers: 1, 2, 3 (1X3), 4, 6 (2×3), 8, 12 (4×3), 16, 24 (8×3), 32, 48 (16×3), 64, 96 (32×3), and 192 (64×3).Default: MP = 0, no multiplicationD2−D0PN2−PN0Number of optical black pixels per line to average = 2NN can be 0, 1, 2, 3, 4, 5, and 6. Or number of pixels per line can be 1, 2, 4, 8 (default), 16, 32, or 64.The maximum number of pixels per line is 64, even if N>6.D7HYSD6D5, D4XSOFW1,SOFW0D3MPDefault optical black calibration register value = 0000000011POST OFFICE BOX 655303 DALLAS, TEXAS 75265•13元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDREGISTER DEFINITIONhot/cold pixel limit register formatD9XD8XD7XD6XD5XD4XD3XD2XD1XD0HFITSLAS326A − JANUARY 2001 − REVISED MARCH 2004hot/cold pixel limit register descriptionBitD9 − D1D0NameXHFITReservedSet hot/cold pixel filter0 − Apply Vb ± .8 hot/cold pixel filtering1 − No hot/cold pixel filtering (default)DescriptionDefault hot/cold pixel limit register value = 0000000001control register2 formatD9SOFD8NOSD7ASOFD6VGNDD5INMD4ACLD3WT3D2WT2D1WT1D0WT0control register 2 descriptionBITD9NAMESOFDESCRIPTION0 – Normal mode (default)1 – Start of frame (only used when exposure time is changed)When this bit is set to 1, next positive ADCCLK edge indicates that next pixel line is the beginning of a new frame.The optical black correction will be performed with one line averaging only (digital filtering weight = 1) and withouthot/cold pixel limits.Internal test bit, add 255 to optical black pixels when this bit is set to 1; default = 0Enable the auto SOF:1 − Automatically enable SOF at major gain changes (no digital filtering for 1 line)0 − No auto SOF (default)Short VIDEOIN to GND when this bit is set to 1; default = 0This bit selects the input modes.0 − CCD mode (default)1 − Video mode0 Video mode, autoclamp (default)1 Video mode, manual clampThese three bits set the weight for digital filtering.WT3WT2WT1WT0Weight (effect of the averaged result of each opticalblack pixel line on overall optical black averaging)0000100011/200101/200111/801001/1601011/3201101/6401111/128 (default)10001/256D8D7NOSASOFD6D5VGNDINMD4D3−D0ACLWT3−WT0Default control register2 value = X00000000014POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004REGISTER DEFINITIONblanking data register formatD90D80D70D60D5BDTAD40D30D20D10D00blanking data register descriptionBITD5NAMEBDTADESCRIPTIONThis register value appears at the digital output when BLKG is low. When this bit is set to 1, digital output during blankingwill be VB. Register default value = 0.Default = 0000000000ADCCLK internal delay register formatD9XD8XD7XD6XD5XD4XD3ADL3D2ADL2D1ADL1D0ADL0ADCCLK internal delay register descriptionBITD9−D4D3−D0NAMEXADL3−ADL0ReservedThese four bits set the internal ADCCLK delay.ADL3ADL2ADL1ADL0Typical internal delay 0 0 0 00 ns (default):: 1 1 1 110 nsDESCRIPTIONDefault register value = XXXXXX0000SR and SV internal delay register formatD9XD8XD7SVL3D6SVL2D5SVL1D4SVL0D3SRL3D2SRL2D1SRL1D0SRL0SR and SV internal delay register descriptionBITD9−D8D7−D4NAMEXSVL3−SVL0ReservedThese four bits set the internal SV delay.SVL3SVL2SVL1SVL0Typical internal delay 0 0 0 00 ns (default):: 1 1 1 110 nsThese four bits set the internal SR delay.SRL3SRL2SRL1SRL0Typical internal delay 0 0 0 00 ns (default):: 1 1 1 110 nsDESCRIPTIOND3−D0SRL3−SRL0Default register value = XX00000000POST OFFICE BOX 655303 DALLAS, TEXAS 75265•15元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDREGISTER DEFINITIONtest register formatD9TB9D8TB8D7TB7D6TB6D5XD4XD3TB3D2TB2D1XD0XSLAS326A − JANUARY 2001 − REVISED MARCH 2004Default register value =0110000000These bits must be set to 1011 for 40 MSPStest register descriptionBITD9−D6NAMETB9−TB6DESCRIPTIONThese four bits are used to program internal DC bias current. The bias current programming uses the following equation:Ibias = 8 µA + (code) × 2 µAHence, Ibias varies from 8 µA (code=0000) to 38 µA (code=1111), with a linear step of 2 µA.Default code is 0110. These bits must be set to 1011 for 40 MSPSD5, D4D3D2TB3TB2Reserved1 – use external reference, power down internal reference0 – use internal reference (default)This bit selects test input mode.0 − Single-ended input on CCDIN pin,1 − Differential input on both CCDIN and VIDEOIN pinsReservedD1, D0PRINCIPLES OF OPERATIONCCD mode operationThe output from the CCD sensor is first fed to a correlated double sampler (CDS) through the CCDIN pin. TheCCD signal is sampled and held during the reset reference interval and the video signal interval. By subtractingtwo resulting voltage levels, the CDS removes low frequency noise from the output of the CCD sensor andobtains the voltage difference between the CCD reference level and the video level of each pixel. Twosample/hold control pulses (SR and SV) are required to perform the CDS function.The CCD output is capacitively coupled to the TLV990-40. The ac-coupling capacitor is clamped to establishproper dc bias during the dummy pixel interval by the CLCCD input. The bias at the input to the TLV990-40 isset to 1.2V. Normally, CLCCD is applied at sensor’s line rate. A capacitor, with a value ten times larger thanthat of the input ac-coupling capacitor, should be connected between the CLREF pin and the AGND.When operating the TLV990-40 at its maximum speed, the CCD internal source resistance should be smallerthan 50 Ω. Otherwise CCD output buffering is required.The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 to 36dBby programming the internal gain register via the serial port. The PGA is digitally controlled with 10-bit resolutionon a linear dB scale, resulting in a 0.045-dB gain step. The gain can be expressed by the following equation,Gain = PGA code × 0.045 dBWhere PGA code has a range of 0 to 767.16POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004PRINCIPLES OF OPERATIONADCThe ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fully-differential implementation and digital-error correction ensure 10-bit resolution.The latency of the ADC data output is 6 ADCCLK cycles, as shown in Figure 1. Pulling the OE pin (pin 24) highputs the ADC output in high impedance.user DACsThe TLV990-40 includes two user DACs that can be used for external analog settings. The output voltage ofeach DAC can be independently set and has a range of 0 V up to the supply voltage, with an 8-bit resolution.When the user DACs are not used in a camera system, they can be put in the standby mode by programmingcontrol bits in the control register.internal timingThe SR and SV signals are required to operate the CDS, as previously explained. The user needs tosynchronize the SR and SV clocks with the CCD signal waveform. The output of the ADC is read out to externalcircuitry by the ADCCLK signal, which is also used internally to control both ADC and PGA operations. It isrequired that the positive half cycle of the ADCCLK signal always falls in between two adjacent SV pulses asshown in Fig. 1. The user can then fine tune the ADCCLK timing in relation to the CDS timing to achieve optimalperformance.The CLCCD signal is used to activate the input clamping and the OBCLP signal is used to activate auto-opticalblack and offset correction.input blanking functionLarge input transients may occur at the TLV990-40’s input during some period of operation which can saturatethe input circuits and cause long recovery time. To prevent circuit saturation the TLV990-40 includes an inputblanking function that blocks the input signals by disabling the CDS operation whenever the BLKG input is pulledlow. The TLV990-40 digital output will be set by the blanking data register after BLKG is pulled low.NOTE:If the BLKG pulse is located before the OBCLP pulse, there must be at least 4 pixels between therising edge of the BLKG pulse and the falling edge of the OBCLP pulse. If the BLKG pulse is locatedafter the OBCLP, the minimum number of pixels between the falling edge of the OBCLP and thefalling edge of the BLKG pulse should be equal to the number of optical black pixels per line + 4.3-wire serial interfaceA simple 3-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the TLV990-40 internalregisters. Serial clock SCLK can be run at a maximum frequency of 40 MHz. Serial data SDIN is 16 bits long.The two leading null bits are followed by four address bits for which the internal register is to be updated, andthen ten bits of data to be written to the register. The CS pin must be held low to enable the serial port. Datatransfer is initiated by the incoming SCLK after CS falls.The SCLK polarity is selectable by pulling the SCKP pin either high or low.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•17元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDPRINCIPLES OF OPERATIONdevice resetWhen pin RESET (pin 29) is pulled low, all internal registers are set to their default values. The device also resetsitself when it is first powered on. In addition, the TLV990-40 has a software-reset function that resets the devicewhen writing a control bit to the control register.See the register definition section for the register default values.SLAS326A − JANUARY 2001 − REVISED MARCH 2004voltage referencesAn internal precision-voltage reference of 1.5 V nominal is provided. This reference voltage is used to generatethe ADC Ref− voltage of 1 V and Ref+ of 2 V. It is also used to set the clamp voltage. All internally-generatedvoltages are fixed values and cannot be adjusted.power-down mode (standby)The TLV990-40 implements both hardware and software power-down modes. Pulling pin STBY (pin 30) lowputs the device in the low-power standby mode. Total supply current drops to about 0.6 mA. Setting apower-down control bit in the control register can also activate the power-down mode. The user can still programall internal registers during the power-down mode.power supplyThe TLV990-40 has several power-supply pins. Each major internal analog block has a dedicated AVDD supplypin. All internal digital circuitry is powered by DVDD. Both AVDD and DVDD are 3-V nominal.The DIVDD and DIGND pins supply power to the output digital driver (D9−D0). The DIVDD is independent of theDVDD and can be operated from 1.8 V to 4.4 V. This allows the outputs to interface with digital ASICs requiringdifferent supply voltages.ground and decouplingAll ground pins of the TLV990-40 are not internally connected and must be connected externally to PCB ground.General practices should apply to the PCB design to limit high-frequency transients and noise that are fed backinto the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.In the case of power supply decoupling, 0.1-µF ceramic chip capacitors are adequate to keep the impedancelow over a wide frequency range. Recommended external decoupling for the three voltage-reference pins isshown in Figure 4. Since their effectiveness depends largely on the proximity to the individual supply pin, alldecoupling capacitors should be placed as close as possible to the supply pins.To reduce high-frequency and noise coupling, it is highly recommended that digital and analog grounds beshorted immediately outside the package. This can be accomplished by running a low-impedance line betweenDGND and AGND under the package.18POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004PRINCIPLES OF OPERATIONautomatic optical black and offset correctionIn the TLV990-40, the optical black and system channel-offset corrections are performed by an autodigitalfeedback loop. Two DACs are used to compensate for both channel offset and optical black offset. A coarsecorrection DAC (CDAC) is located before PGA gain stage, and a fine correction DAC (FDAC) is located afterthe gain stage. The digital-calibration system is capable of correcting the optical black and channel offset downto one ADC LSB accuracy.The TLV990-40 automatically starts autocalibration whenever the OBCLP input is pulled low. The OBCLP pulseshould be wide enough to cover one positive half cycle of the ADCCLK, as shown in Figure 1.For each line, the optical black pixels plus the channel offset are sampled and converted to digital data by theADC. A digital circuit averages the data during the optical black pixels. The averaged result is compared digitallywith the desired output code stored in the Vb register (default is 40H), then the FDAC is adjusted by control logicto make the ADC output equal to the Vb. If the offset is out of the range of the FDAC (±225 ADC LSBs), the erroris corrected by both the CDAC and the FDAC. The CDAC increments or decrements by one CDAC LSB,depending on whether the offset is negative of positive, until the output is within the range of the FDAC. Theremaining residue is corrected by the FDAC.The relationship among the FDAC, CDAC, and ADC in terms of number of ADC LSBs is as follows:1 FDAC LSB = 1 ADC LSB,1 CDAC LSB = PGA linear gain × n ADC LSBwhere n is: 4 for 0 ≤ gain code < 641.5 for 64 ≤ gain code < 96 1 for 96 ≤ gain code < 128 1 for 128 ≤ gain codeFor example, if PGA gain = 2 (6 dB), then, 1 CDAC LSB = 2 x 4 ADC LSBs = 8 ADC LSBs.After autocalibration is complete, the ADC’s digital output during CCD signal interval can be expressed by thefollowing equation:ADC output [D9−D0] = CCD_input × PGA gain + Vb,Where Vb is the desired black level selected by user. The total offset, including optical black offset, is calibratedto be equal to the Vb by adjusting the offset correction DACs during autocalibration.A weighted rolling average of the optical black pixels is taken during averaging. The weighting factor can beprogrammed in control register2. The weighting factor determines the speed of convergence of the digitalfiltering implemented within the CCD signal processor. Weighting factors closer to 1 result in fasterconvergence. As the weighting factor decreases towards its minimum value of 1/128, the speed of convergenceof the digital filtering decreases.The algorithm also takes hot pixels and cold pixels into consideration. A hot optical black pixel is a defectivepixel that generates too much charge, while a cold pixel is the one that generates very little or no charge. A digitalcomparator compares the digitized optical black pixels with user-selected hot and cold pixel limits. If the opticalblack pixel value is out of range, then that hot or cold pixel is replaced with the value of the previous pixel.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•19元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDPRINCIPLES OF OPERATIONautomatic optical black and offset correction (continued)Due to different exposure times, there might be a sudden optical black level shift at the start of each frame. Thus,a quick optical black level correction is desirable. The user can set an internal control bit (the SOF bit in controlregister2) to automatically disable the hot/cold pixel limits and to set the digital filtering weighting factor to 1(equivalent to one-line averaging). In this way the optical black correction could be performed very quickly forthe first line of each frame.The number of black pixels in each line is programmable. The number of black pixels per line that can beaveraged is 2N, where N can be any integer from 0 to 6.The autocalibration feature can be bypassed if the user prefers to directly program the offset DAC registers.Switching the autocalibration mode to the direct-programming mode requires two register writes. First, thecontrol bits for the offset DACs in the control register must be changed, then the desired offset value for theregister is loaded to the offset DAC registers for proper error correction. If the total offset, including optical blacklevel is less than ±255 ADC LSBs, only the FDAC needs to be programmed. When switching from direct-programming mode to autocalibration mode, the previous DAC register values, rather than default DAC registervalues, are used as starting offsets.SLAS326A − JANUARY 2001 − REVISED MARCH 200420POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comTLV990Ć403ĆV, 10ĆBIT, 40ĆMSPS AREA CCD ANALOG FRONTĆENDSLAS326A − JANUARY 2001 − REVISED MARCH 2004MECHANICAL DATAPFB (S-PQFP-G48) PLASTIC QUAD FLATPACK0,5036250,270,170,08M372448130,13 NOM15,50 TYP7,20SQ6,809,20SQ8,800,05 MIN1,050,95Seating Plane0,750,45Gage Plane0,250°−7°121,20 MAX0,084073176/B 10/96NOTES:A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Falls within JEDEC MS-026POST OFFICE BOX 655303 DALLAS, TEXAS 75265•21元器件交易网www.cecb2b.com
PACKAGEOPTIONADDENDUM
www.ti.com
4-Nov-2005
PACKAGINGINFORMATION
OrderableDeviceTLV990-40PFBTLV990-40PFBG4
(1)
Status(1)ACTIVEACTIVE
PackageTypeTQFPTQFP
PackageDrawingPFBPFB
PinsPackageEcoPlan(2)
Qty4848
250250
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-2-260C-1YEARLevel-2-260C-1YEAR
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS)orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
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Addendum-Page1
元器件交易网www.cecb2b.com MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK0,5036250,270,170,08M372448130,13 NOM15,50 TYP7,20SQ6,809,20SQ8,800,05 MIN1,050,95Seating Plane0,750,45Gage Plane0,250°–7°121,20 MAX0,084073176/B 10/96NOTES:A.All linear dimensions are in millimeters.B.This drawing is subject to change without notice.C.Falls within JEDEC MS-026POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
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