Cache memory system

专利名称：Cache memory system发明人：Hiroyuki Usui申请号：US12432883申请日：20090430公开号：US08108611B2公开日：20120131

专利附图：

摘要：A cache memory system controlled by an arbiter includes a memory unit havinga cache memory whose capacity is changeable, and an invalidation processing unit thatrequests invalidation of data stored at a position where invalidation is performed whenthe capacity of the cache memory is changed in accordance with a change instruction. The

invalidation processing unit includes an increasing/reducing processing unit that sets anindex to be invalidated in accordance with a capacity before change and a capacity afterchange and requests the arbiter to invalidate the set index, and an index converter thatselects either an index based on the capacity before change or an index based on thecapacity after change associated with an access address from the arbiter, and the capacityof the cache memory can be changed while maintaining the number of ways of the cachememory.

申请人：Hiroyuki Usui

地址：Fuchu JP

国籍：JP

代理机构：Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.

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