专利名称：Clock Generating Circuit发明人：Mitsuru Ooyagi,Tomoaki Nishi申请号：US12691530申请日：20100121
公开号：US20100182066A1公开日：20100722
专利附图：
摘要：A main (sub) clock circuit comprising a first (second) capacitor, a first (second)current-supply circuit to supply to the first (second) capacitor a first (third) current forcharging at a predetermined-current value or a second (fourth) current for discharging ata predetermined-current value, a first (second) charge/discharge-control circuit to output
a first (second) control signal for switching between the first (third) current and second(fourth) current which are supplied to the first (second) capacitor from the first (second)current-supply circuit when a voltage across the first (second) capacitor has reached afirst (third) reference voltage or second (fourth) reference voltage higher than the first(third) reference voltage, and a first (second) output circuit to output a main (sub) clockaccording to the first (second) control signal, the first capacitor having one endconnected to a first potential, the second capacitor having one end to which the mainclock is input.
申请人：Mitsuru Ooyagi,Tomoaki Nishi
地址：Fukaya-City JP,Nagaoka-City JP
国籍：JP,JP
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