用VHDL实现二位二进制乘法应用译码器

用VHDL实现二位二进制乘法应用译码器

文件管理序列号：[K8UY-K9IO69-O6M243-OL8-F88688]

---------------------------------------------------------------------------------- -- Company: -- Engineer: --

-- Create Date: 18:25:21 04/15/2013 -- Design Name:

-- Module Name: FOUR - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --

-- Dependencies: --

-- Revision:

-- Revision 0.01 - File Created -- Additional Comments: --

---------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_11.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; entity FOUR is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC; d : in STD_LOGIC; DOUT : out std_logic_vector(3 downto

0));

end FOUR;

architecture Behavioral of FOUR is

signal DIN :STD_LOGIC_VECTOR(3 DOWNTO 0);

signal y : std_logic_vector(16 downto 0); begin

DIN <= A & B & C & D; process (A,B,C,D) begin

case DIN is

when \"0000\" => y(0) <= '0'; when \"0001\" => y(1) <= '0'; when \"0010\" => y(2) <= '0'; when \"0011\" => y(3) <= '0'; when \"0100\" => y(4) <= '0'; when \"0101\" => y(5) <= '0'; when \"0110\" => y(6) <= '0'; when \"0111\" => y(7) <= '0'; when \"1000\" => y(8) <= '0'; when \"1001\" => y(9) <= '0'; when \"1010\" => y(10) <= '0'; when \"1011\" => y(11) <= '0'; when \"1100\" => y(12) <= '0'; when \"1101\" => y(13) <= '0'; when \"1110\" => y(14) <= '0'; when \"1111\" => y(15) <= '0'; when others => y(16) <= '0';

end case ; end process;

DIN(3)<=not(y(15));

DIN(2)<=not(y(10) and y(11) and y(14));

DIN(1)<=not(y(6) and y(7) and y(9)and y(11) and y(13) and y(14)); DIN(0)<=not(y(5)and y(7) and y(13) and y(15)); end Behavioral;