USB 是 Universal Serial Bus 的缩写，由 Compaq, Digital, IBM, Intel, Microsoft, NEC, Northern Telecom 联合推出。外观上计算机一侧为 4 针公插，设备一侧为 4 针母插。 引脚定义
Pin Name Description 1 2 3 4 VCC +5 VDC D- D+ Data - Data + GND Ground
AGP总线定义
AGP 是 Accelerated Graphics Port，是 Intel 推出的一种 3D 图形标准接口，它能够提供四倍于 PCI 的效率，AGP2X 的传输速率达到 533MB。有关 AGP 的说明可以在 Intel 的网站上找到。 引脚定义
Pin 1 2 3 4 5 6 7 8 9 Spare 5.0V 5.0V USB+ Ground INTB# Clock REQ# Vcc3.3V B面 12V Spare Reserved USB- Ground INTA# RST# GNT# Vcc3.3V A面 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 ST0 ST2 RBF# Ground Spare SBA0 Vcc3.3V SBA2 SB_STB Ground SBA4 SBA6 Key Key Key Key Address31 Address29 Vcc3.3V Address27 Address25 Ground AD_STB1 Address23 Vddq3.3 Address21 Address19 Ground Address17 C/BE2# Vddq3.3 IRDY# Ground Vcc3.3V ST1 Reserved PIPE# Ground Spare SBA1 Vcc3.3V SBA3 Reserved Ground SBA5 SBA7 Key Key Key Key Address30 Address28 Vcc3.3V Address26 Address24 Ground Reserved C/BE3# Vddq3.3 Address22 Address20 Ground Address18 Address16 Vddq3.3 FRAME# Ground Vcc3.3V 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 DEVSEL# Vddq3.3 Perr# Ground SERR# C/BE1# Vddq3.3 Address14 Address12 Ground Address10 Address8 Vddq3.3 AD_STB0 Address7 Ground Address5 Address3 Vddq3.3 Address1 SMB0 TRDY# STOP# Spare Ground PAR Address15 Vddq3.3 Address13 Address11 Ground Address9 C/BE0# Vddq3.3 Reserved Address6 Ground Address4 Address2 Vddq3.3 Address0 SMB1
PCI总线定义
PCI 是 Peripheral Component Interconnect 的缩写 接口卡的外观
PCI 标准 32位/64位 接口卡
---------------------------------------------------------------- | PCI 元件侧 （B面） | | | | | | | | ____ 32 位引脚部分 64 位引脚部分 ___| |___| |||||||--|||||||||||||||||--|||||||--|||||||||||||| ^ ^ ^ ^ ^ ^ ^ ^
b01 b11 b14 b49 b52 b62 b63 b94 PCI 5V 32/64位卡
| optional | | ____ 32 位引脚部分 64 位引脚部分 ___| |___| ||||||||||||||||||||||||||--|||||||--|||||||||||||| PCI 3.3V 32/64位卡
| optional | | ____ 32 位引脚部分 64 位引脚部分 ___| |___| |||||||--||||||||||||||||||||||||||--||||||||||||||
引脚定义
Pin +5V +3.3V Universal Description Test Logic Reset +12 VDC Test Mde Select Test Data Input +5 VDC Interrupt A Interrupt C +5 VDC Reserved VDC A1 TRST A2 +12V A3 TMS A4 TDI A5 +5V A6 INTA A7 INTC A8 +5V A9 RESV01 A10 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Reserved VDC Ground or Open (Key) Ground or Open (Key) Reserved VDC Reset A11 RESV03 A12 GND03 (OPEN) (OPEN) A13 GND05 (OPEN) (OPEN) A14 RESV05 A15 RESET A16 +5V A17 GNT +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Grant PCI use Ground Reserved VDC Address/Data 30 +3.3 VDC Address/Data 28 Address/Data 26 Ground A18 GND08 A19 RESV06 A20 AD30 A21 +3.3V01 A22 AD28 A23 AD26 A24 GND10 A25 AD24 A26 IDSEL Address/Data 24 Initialization Device Select +3.3 VDC Address/Data 22 Address/Data 20 Ground Address/Data 18 Address/Data 16 +3.3 VDC Address or Data phase Ground Target Ready Ground Stop Transfer Cycle +3.3 VDC Snoop Done Snoop Backoff Ground Parity Address/Data 15 +3.3 VDC Address/Data 13 Address/Data 11 Ground Address/Data 9 Command, Byte Enable 0 +3.3 VDC Address/Data 6 Address/Data 4 Ground Address/Data 2 Address/Data 0 A27 +3.3V03 A28 AD22 A29 AD20 A30 GND12 A31 AD18 A32 AD16 A33 +3.3V05 A34 FRAME A35 GND14 A36 TRDY A37 GND15 A38 STOP A39 +3.3V07 A40 SDONE A41 SBO A42 GND17 A43 PAR A44 AD15 A45 +3.3V10 A46 AD13 A47 AD11 A48 GND19 A49 AD9 A52 C/BE0 A53 +3.3V11 A54 AD6 A55 AD4 A56 GND21 A57 AD2 A58 AD0 A59 +5V A60 REQ64 +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Request 64 bit ??? +5 VDC +5 VDC A61 VCC11 A62 VCC13 A63 GND Ground Command, Byte Enable 7 Command, Byte Enable 5 A64 C/BE[7]# A65 C/BE[5]# A66 +5V A67 PAR64 A68 AD62 A69 GND A70 AD60 A71 AD58 A72 GND A73 AD56 A74 AD54 A75 +5V A76 AD52 A77 AD50 A78 GND A79 AD48 A80 AD46 A81 GND A82 AD44 A83 AD42 A84 +5V A85 AD40 A86 AD38 A87 GND A88 AD36 A89 AD34 A90 GND A91 AD32 A92 RES A93 GND A94 RES B1 -12V B2 TCK +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Parity 64 ??? Address/Data 62 Ground Address/Data 60 Address/Data 58 Ground Address/Data 56 Address/Data 54 +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Address/Data 52 Address/Data 50 Ground Address/Data 48 Address/Data 46 Ground Address/Data 44 Address/Data 42 +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Address/Data 40 Address/Data 38 Ground Address/Data 36 Address/Data 34 Ground Address/Data 32 Reserved Ground Reserved -12 VDC Test Clock B3 GND B4 TDO B5 +5V B6 +5V B7 INTB B8 INTD Ground Test Data Output +5 VDC +5 VDC Interrupt B Interrupt D Reserved +V I/O (+5 V or +3.3 V) ?? Ground or Open (Key) Ground or Open (Key) Reserved VDC Reset Clock Ground Request B9 PRSNT1 B10 RES B11 PRSNT2 B12 GND B13 GND B14 RES B15 GND B16 CLK B17 GND B18 REQ B19 +5V B20 AD31 B21 AD29 B22 GND B23 AD27 B24 AD25 B25 +3.3V B26 C/BE3 B27 AD23 B28 GND B29 AD21 B30 AD19 B31 +3.3V B32 AD17 B33 C/BE2 (OPEN) (OPEN) (OPEN) (OPEN) +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Address/Data 31 Address/Data 29 Ground Address/Data 27 Address/Data 25 +3.3VDC Command, Byte Enable 3 Address/Data 23 Ground Address/Data 21 Address/Data 19 +3.3 VDC Address/Data 17 Command, Byte Enable 2 Ground Initiator Ready +3.3 VDC Device Select Ground B34 GND13 B35 IRDY B36 +3.3V06 B37 DEVSEL B38 GND16 B39 LOCK B40 PERR (OPEN) (OPEN) Lock bus Parity Error +3.3 VDC System Error +3.3 VDC Command, Byte Enable 1 Address/Data 14 Ground Address/Data 12 Address/Data 10 Ground Ground or Open (Key) Ground or Open (Key) Address/Data 8 Address/Data 7 +3.3 VDC Address/Data 5 Address/Data 3 Ground Address/Data 1 +5 VDC Acknowledge 64 bit ??? +5 VDC +5 VDC Reserved Ground Command, Byte Enable 6 Command, Byte Enable 4 Ground Address/Data 63 Address/Data 61 B41 +3.3V08 B42 SERR B43 +3.3V09 B44 C/BE1 B45 AD14 B46 GND18 B47 AD12 B48 AD10 B49 GND20 B50 (OPEN) GND B51 (OPEN) GND B52 AD8 B53 AD7 B54 +3.3V12 B55 AD5 B56 AD3 B57 GND22 B58 AD1 B59 VCC08 B60 ACK64 B61 VCC10 B62 VCC12 B63 RES B64 GND B65 C/BE[6]# B66 C/BE[4]# B67 GND B68 AD63 B69 AD61 B70 +5V B71 AD59 B72 AD57 B73 GND +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Address/Data 59 Address/Data 57 Ground B74 AD55 B75 AD53 B76 GND B77 AD51 B78 AD49 B79 +5V B80 AD47 B81 AD45 B82 GND B83 AD43 B84 AD41 B85 GND B86 AD39 B87 AD37 B88 +5V B89 AD35 B90 AD33 B91 GND B92 RES B93 RES B94 GND Address/Data 55 Address/Data 53 Ground Address/Data 51 Address/Data 49 +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Address/Data 47 Address/Data 45 Ground Address/Data 43 Address/Data 41 Ground Address/Data 39 Address/Data 37 +3.3V Signal Rail +V I/O (+5 V or +3.3 V) Address/Data 35 Address/Data 33 Ground Reserved Reserved Ground
ISA 总线定义
ISA 是 Industry Standard Architecture 的缩写 接口卡的外观
插槽的外观
引脚定义
引脚 定义 方向 说明 I/O channel check; active low=parity error Data bit 7 Data bit 6 Data bit 5 Data bit 4 Data bit 3 Data bit 2 Data bit 1 Data bit 0 I/O Channel ready, pulled low to lengthen memory cycles Address enable; active high when DMA controls bus Address bit 19 Address bit 18 Address bit 17 Address bit 16 A1 /I/O CH CK A2 D7 A3 D6 A4 D5 A5 D4 A6 D3 A7 D2 A8 D1 A9 D0 A10 I/O CH RDY A11 AEN A12 A19 A13 A18 A14 A17 A15 A16 A16 A15 A17 A14 A18 A13 A19 A12 A20 A11 A21 A10 A22 A9 A23 A8 A24 A7 A25 A6 A26 A5 A27 A4 A28 A3 A29 A2 A30 A1 A31 A0 B1 B2 B3 B4 B5 B6 B7 B8 B9 GND RESET +5V IRQ2 -5VDC DRQ2 -12VDC /NOWS +12VDC Address bit 15 Address bit 14 Address bit 13 Address bit 12 Address bit 11 Address bit 10 Address bit 9 Address bit 8 Address bit 7 Address bit 6 Address bit 5 Address bit 4 Address bit 3 Address bit 2 Address bit 1 Address bit 0 Ground Active high to reset or initialize system logic +5 VDC Interrupt Request 2 -5 VDC DMA Request 2 -12 VDC No WaitState +12 VDC Ground System Memory Write System Memory Read I/O Write I/O Read DMA Acknowledge 3 DMA Request 3 DMA Acknowledge 1 DMA Request 1 Refresh System Clock (67 ns, 8-8.33 MHz, 50% duty cycle) B10 GND B11 /SMEMW B12 /SMEMR B13 /IOW B14 /IOR B15 /DACK3 B16 DRQ3 B17 /DACK1 B18 DRQ1 B19 /REFRESH B20 CLOCK B21 IRQ7 B22 IRQ6 B23 IRQ5 B24 IRQ4 B25 IRQ3 B26 /DACK2 B27 T/C B28 ALE B29 +5V B30 OSC B31 GND C1 C2 C3 C4 C5 C6 C7 C8 C9 SBHE LA23 LA22 LA21 LA20 LA18 LA17 LA16 /MEMR Interrupt Request 7 Interrupt Request 6 Interrupt Request 5 Interrupt Request 4 Interrupt Request 3 DMA Acknowledge 2 Terminal count; pulses high when DMA term. count reached Address Latch Enable +5 VDC High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle) Ground System bus high enable (data available on SD8-15) Address bit 23 Address bit 22 Address bit 21 Address bit 20 Address bit 19 Address bit 18 Address bit 17 Memory Read (Active on all memory read cycles) Memory Write (Active on all memory write cycles) Data bit 8 Data bit 9 Data bit 10 Data bit 11 Data bit 12 Data bit 13 Data bit 14 Data bit 15 Memory 16-bit chip select (1 wait, 16-bit memory cycle) I/O 16-bit chip select (1 wait, 16-bit I/O cycle) Interrupt Request 10 Interrupt Request 11 Interrupt Request 12 Interrupt Request 15 C10 /MEMW C11 SD08 C12 SD09 C13 SD10 C14 SD11 C15 SD12 C16 SD13 C17 SD14 C18 SD15 D1 /MEMCS16 D2 /IOCS16 D3 IRQ10 D4 IRQ11 D5 IRQ12 D6 IRQ15 D7 IRQ14 D8 /DACK0 D9 DRQ0 D10 /DACK5 D11 DRQ5 D12 /DACK6 D13 DRQ6 D14 /DACK7 D15 DRQ7 D16 +5 V D17 /MASTER D18 GND Interrupt Request 14 DMA Acknowledge 0 DMA Request 0 DMA Acknowledge 5 DMA Request 5 DMA Acknowledge 6 DMA Request 6 DMA Acknowledge 7 DMA Request 7 Used with DRQ to gain control of system Ground
EISA总线定义
EISA 是 Extended Industry Standard Architecture 的缩写，由 Compaq, AST, Zenith, Tandy 等公司开发。 接口卡的外观
+---------------------------------------------+ | 元件面 | | | |___________ ISA-16bit __ ISA-8bit __|
||||||||||| ||||||||||||||||||| A1 正面/B1 反面
| | | | | | | | | | | | | | EISA: E1 正面/F1 反面 C1/D1 G1/H1 A,C,E,G=元件面 A,B,F,H=线路面
引脚定义
Pin E1 E2 E3 CMD# START# EXRDY Name Command Phase Start Phase EISA Ready Description E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 F1 F2 F3 F4 F5 F6 F7 EX32# GND KEY EX16# SLBURST# MSBURST# W/R# GND RES RES RES GND KEY BE1# LA31# GND LA30# LA28# LA27# LA25# GND KEY LA15 LA13 LA12 LA11 GND LA9 GND +5V +5V --- --- KEY --- EISA Slave Size 32 Ground Access Key EISA Slave Size 16 Slave Burst Master Burst Write/Read Ground Reserved Reserved Reserved Ground Access Key Byte Enable 1 Latchable Addressline 31 Ground Latchable Addressline 30 Latchable Addressline 28 Latchable Addressline 27 Latchable Addressline 25 Ground Access Key Latchable Addressline 15 Latchable Addressline 13 Latchable Addressline 12 Latchable Addressline 11 Ground Latchable Addressline 9 Ground +5 VDC +5 VDC Access Key F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 --- +12V M/IO# LOCK# RES GND RES BE3# KEY BE2# BE0# GND +5V LA29# GND LA26# LA24# KEY LA16 LA14 +5V +5V GND LA10 LA7 GND LA4 LA3 GND KEY D17 D19 D20 D22 GND +12 VDC Memory/Input-Output Lock bus Reserved Ground Reserved Byte Enable 3 Access Key Byte Enable 2 Byte Enable 0 Ground +5 VDC Latchable Addressline 29 Ground Latchable Addressline 26 Latchable Addressline 24 Access Key Latchable Addressline 16 Latchable Addressline 14 +5 VDC +5 VDC Ground Latchable Addressline 10 Latchable Addressline 7 Ground Latchable Addressline 4 Latchable Addressline 3 Ground Access Key Data 17 Data 19 Data 20 Data 22 Ground G12 G13 G14 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 D25 D26 D28 KEY GND D30 D31 MREQx LA8 LA6 LA5 +5V LA2 KEY D16 D18 GND D21 D23 D24 GND D27 KEY D29 +5V +5V Data 25 Data 26 Data 28 Access Key Ground Data 30 Data 31 Master Request Latchable Addressline 8 Latchable Addressline 6 Latchable Addressline 5 +5 VDC Latchable Addressline 2 Access Key Data 16 Data 18 Ground Data 21 Data 23 Data 24 Ground Data 27 Access Key Data 29 +5 VDC +5 VDC
PCMCIA引脚定义
PCMCIA 是 Personal Computer Memory Card International AssociationIndustry Standard Architecture 的缩写，是便携式计算机外扩卡的接口定义。
引脚定义
Pin 1 2 3 4 5 6 7 8 9 Name GND D3 D4 D5 D6 D7 /CE1 A10 /OE Dir Ground Data 3 Data 4 Data 5 Data 6 Data 7 Description Card Enable 1 Address 10 Output Enable Address 11 Address 9 Address 8 Address 13 Address 14 Write Enable : Program Ready : Busy (IREQ) +5V Programming Voltage (EPROM) Address 16 Address 15 Address 12 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data 0 Data 1 10 A11 11 A9 12 A8 13 A13 14 A14 15 /WE:/P 16 /READY:/IREQ 17 VCC 18 VPP1 19 A16 20 A15 21 A12 22 A7 23 A6 24 A5 25 A4 26 A3 27 A2 28 A1 29 A0 30 D0 31 D1 32 D2 33 /WP:/IOIS16 34 GND 35 GND 36 /CD1 37 D11 38 D12 39 D13 40 D14 41 D15 42 /CE2 43 /VS1 44 /IORD 45 /IOWR 46 A17 47 A18 48 A19 49 A20 50 A21 51 VCC 52 VPP2 53 A22 54 A23 55 A24 56 A25 57 /VS2 58 RESET 59 /WAIT 60 /INPACK 61 /REG 62 /BVD2:SPKR 63 /BVD1:STSCHG 64 D8 65 D9 66 D10 67 /CD2 ? ? ? ? ? ? Data 2 Write Protect : IOIS16 Ground Ground Card Detect 1 Data 11 Data 12 Data 13 Data 14 Data 15 Card Enable 2 Refresh I/O Read I/O Write Address 17 Address 18 Address 19 Address 20 Address 21 +5V Programmeing Voltage 2 (EPROM) Address 22 Address 23 Address 24 Address 25 RFU RESET WAIT Register Select Battery Voltage Detect 2 : SPKR Battery Voltage Detect 1 : STSCHG Data 8 Data 9 Data 10 Card Detect 2 68 GND Ground
VESA总线定义
VESA 是 Video Electronics Standards Association 的缩写，本页列出的是扩展部分的引脚定义，非扩展部分请见 ISA 总线的定义。 接口卡的外观
插槽的外观
引脚定义
Pin Name Data 1 Data 3 Description A1 D1 A2 D3 A3 GND A4 D5 A5 D7 A6 D9 Ground Data 5 Data 7 Data 9 A7 D11 A8 D13 A9 D15 A10 GND A11 D17 A12 Vcc A13 D19 A14 D21 A15 D23 A16 D25 A17 GND A18 D27 A19 D29 A20 D31 A21 A30 A22 A28 A23 A26 A24 GND A25 A24 A26 A22 A27 VCC A28 A20 A29 A18 A30 A16 A31 A14 A32 A12 A33 A10 A34 A8 A35 GND A36 A6 A37 A4 Data 11 Data 13 Data 15 Ground Data 17 +5 VDC Data 19 Data 21 Data 23 Data 25 Ground Data 27 Data 2 Data 31 Address 30 Address 28 Address 26 Ground Address 24 Address 22 +5 VDC Address 20 Address 18 Address 16 Address 14 Address 12 Address 10 Address 8 Ground Address 6 Address 4 A38 WBACK# Write Back A39 BE0# A40 VCC A41 BE1# A42 BE2# Byte Enable 0 +5 VDC Byte Enable 1 Byte Enable 2 A43 GND A44 BE3# A45 ADS# A48 LRDY# A49 LDEV A50 LREQ A51 GND A52 LGNT A53 VCC A54 ID2 A55 ID3 A56 ID4 A57 LKEN# A58 LEADS# B1 D0 B2 D2 B3 D4 B4 D6 B5 D8 B6 GND B7 D10 B8 D12 B9 VCC B10 D14 B11 D16 B12 D18 B13 D20 B14 GND B15 D22 B16 D24 B17 D26 B18 D28 B19 D30 B20 VCC Ground Byte Enable 3 Address Strobe Local Ready Local Device Local Request Ground Local Grant +5 VDC Identification 2 Identification 3 Identification 4 Local Enable Address Strobe Data 0 Data 2 Data 4 Data 6 Data 8 Ground Data 10 Data 12 +5 VDC Data 14 Data 16 Data 18 Data 20 Ground Data 22 Data 24 Data 26 Data 28 Data 30 +5 VDC B21 A31 B22 GND B23 A29 B24 A27 B25 A25 B26 A23 B27 A21 B28 A19 B29 GND B30 A17 B31 A15 B32 VCC B33 A13 B34 A11 B35 A9 B36 A7 B37 A5 B38 GND B39 A3 B40 A2 B41 n/c B42 RESET# B43 DC# B44 M/IO# B45 W/R# Address 31 Ground Address 29 Address 27 Address 25 Address 23 Address 21 Address 19 Ground Address 17 Address 15 +5 VDC Address 13 Address 11 Address 9 Address 7 Address 5 Ground Address 3 Address 2 Not connected Reset Data/Command Memory/IO Write/Read B48 RDYRTN# Ready Return B49 GND B50 IRQ9 B51 BRDY# B52 BLAST# B53 ID0 B54 ID1 B55 GND B56 LCLK B57 VCC Ground Interrupt 9 Burst Ready Burst Last Identification 0 Identification 1 Ground Local Clock +5 VDC B58 LBS16# Local Bus Size 16
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